AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 747

• Manufacturer Part Number: AT91SAM9RL64-CU
• Description: IC ARM9 MCU 217-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9RL64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 118
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 118
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 41-11. Autovalid with DMA
Note:
41.4.8.7
41.4.8.8
6289C–ATARM–28-May-09
In the illustration above Autovalid validates a bank as full, although this might not be the case, in order to continue processing
data and to send to DMA.
Bank (system)
Write
Bank (usb)
Virtual TX_PK_RDY Bank 0
Virtual TX_PK_RDY Bank 1
TX_PK_RDY
(Virtual 0 & Virtual 1)
Isochronous IN
High Bandwidth Isochronous Endpoint Handling: IN Example
Bank 1
Bank 0
write bank 0
Bank 0
Isochronous-IN is used to transmit a stream of data whose timing is implied by the delivery rate.
Isochronous transfer provides periodic, continuous communication between host and device.
It guarantees bandwidth and low latencies appropriate for telephony, audio, video, etc.
If the endpoint is not available (TX_PK_RDY = 0), then the device does not answer to the host.
An ERR_FL_ISO interrupt is generated in the UDPHS_EPTSTAx register and once enabled,
then sent to the CPU.
The STALL_SNT command bit is not used for an ISO-IN endpoint.
For high bandwidth isochronous endpoints, the DMA can be programmed with the number of
transactions (BUFF_LENGTH field in UDPHS_DMACONTROLx) and the system should provide
bank 0 is full
write bank 1
Bank 1
Bank 0
bank 1 is full
IN data 0
AT91SAM9R64/RL64 Preliminary
Bank 0
write bank 0
bank 0 is full
Bank 1
IN data 1
Bank 1
Bank 0
IN data 0
Bank 1
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