AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 586

• Manufacturer Part Number: AT91SAM9RL64-CU
• Description: IC ARM9 MCU 217-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9RL64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 118
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 118
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 37-10. Multi-buffer DMAC Transfer with Source Address Auto-reloaded and Linked List Destination Address
6289C–ATARM–28-May-09
Address of
Source Layer
The DMAC Transfer flow is shown in
18. The DMAC fetches the next LLI from memory location pointed to by the current
SADDR
detect when the transfer is complete. If the DMAC is not in Row 1 as shown in
1 on page
DMAC_DSCRx register, and automatically reprograms the DMAC_DADDRx,
DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel registers. Note that the
DMAC_SADDRx is not re-programmed as the reloaded value is used for the next
DMAC buffer transfer. If the next buffer is the last buffer of the DMAC transfer then the
DMAC_CTRLBx and DMAC_DSCRx registers just fetched from the LLI should match
Row 1 of
ure 37-10 on page
Source Buffers
Table 37-1 on page
575, the following step is performed.
586.
AT91SAM9R64/RL64 Preliminary
575. The DMAC transfer might look like that shown in
Figure 37-11 on page
DADDR(N)
DADDR(0)
DADDR(2)
DADDR(1)
Buffer1
Destination Buffers
Buffer0
Buffer2
BufferN
Destination Layer
587.
Address of
Table 37-
Fig-
586