AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 229

• Manufacturer Part Number: AT91SAM9RL64-CU
• Description: IC ARM9 MCU 217-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9RL64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 118
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 118
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24. Error Corrected Code (ECC) Controller
24.1
24.2
Figure 24-1. Block Diagram
24.3
6289C–ATARM–28-May-09
Description
Block Diagram
Functional Description
NAND Flash/SmartMedia devices contain by default invalid blocks which have one or more
invalid bits. Over the NAND Flash/SmartMedia lifetime, additional invalid blocks may occur
which can be detected/corrected by ECC code.
The ECC Controller is a mechanism that encodes data in a manner that makes possible the
identification and correction of certain errors in data. The ECC controller is capable of single bit
error correction and 2-bit random detection. When NAND Flash/SmartMedia have more than 2
bits of errors, the data cannot be corrected.
The ECC user interface is compliant with the ARM Advanced Peripheral Bus (APB rev2).
A page in NAND Flash and SmartMedia memories contains an area for main data and an addi-
tional area used for redundancy (ECC). The page is organized in 8-bit or 16-bit words. The page
size corresponds to the number of words in the main area plus the number of words in the extra
area used for redundancy.
Controller
Memory
APB
Static
Ctrl/ECC Algorithm
User Interface
Controller
ECC
AT91SAM9R64/RL64 Preliminary
NAND Flash
SmartMedia
Logic
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