AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 18
AT91SAM9RL64-CU
Manufacturer Part Number
AT91SAM9RL64-CU
Description
IC ARM9 MCU 217-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9RL64-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, LCD, POR, PWM, WDT
Number Of I /o
118
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
72K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
2-Wire, SPI, SSC, USART
Maximum Clock Frequency
240 MHz
Number Of Programmable I/os
118
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Controller Family/series
AT91SAM9xxx
No. Of I/o's
118
Ram Memory Size
64KB
Cpu Speed
240MHz
No. Of Timers
1
Rohs Compliant
Yes
Package
217LFBGA
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
240 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Manufacturer:
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Quantity:
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6. I/O Line Considerations
6.1
6.2
6.3
6.4
6.5
7. Processor and Architecture
7.1
18
JTAG Port Pins
Test Pin
Reset Pins
PIO Controllers
Shutdown Logic Pins
ARM926EJ-S Processor
AT91SAM9R64/RL64 Preliminary
TMS, TDI and TCK are schmitt trigger inputs and have no pull-up resistors.
TDO is an output, driven at up to VDDIOP, and have no pull-up resistor.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It
integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left uncon-
nected for normal operations.
All the JTAG signals are supplied with VDDIOP except JTAGSEL supplied by VDDBU.
The TST pin is used for manufacturing test purposes when asserted high. It integrates a perma-
nent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal
operations. Driving this line at a high level leads to unpredictable results.
This pin is supplied with VDDBU.
NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven
with voltage at up to VDDIOP.
As the product integrates power-on reset cells, which manages the processor and the JTAG
reset, the NRST and NTRST pin can be left unconnected.
The NRST and NTRST pins integrates a permanent pull-up resistor of 100 kΩ typical to
VDDIOP.
The NRST signal is inserted in the Boundary Scan.
All the I/O lines which are managed by the PIO Controllers integrate a programmable pull-up
resistor. Refer to the section “AT91SAM9R64/RL64 Electrical Characteristics” in the product
datasheet for more details.
After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which
are multiplexed with the External Bus Interface signals that require to be enabled as Peripheral
at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing
tables.
The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU.
•
•
RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java
acceleration
Two Instruction Sets
6289C–ATARM–28-May-09
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