AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 714

• Manufacturer Part Number: AT91SAM9RL64-CU
• Description: IC ARM9 MCU 217-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9RL64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 118
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 118
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 40-6. Audio Transfer (PCM L Front, PCM R Front) on Channel x
40.6.2.5
40.6.2.6
714
Read access to
(Codec output)
AC97C_RHRx
(AC97C_SR)
RXRDYCx
AC97RX
AC97FS
AT91SAM9R64/RL64 Preliminary
Slot #
AC‘97 Input Frame
Configuring and Using Interrupts
TAG
0
The application can also wait for an interrupt notice in order to read data from AC97C_CxRHR.
The interrupt remains active until RXRDY is cleared by reading AC97C_CxSR.
The RXRDY flag in AC97C_CxSR is set automatically when data is received in the Channel x
shift register. Data is then shifted to AC97C_CxRHR.
If the previously received data has not been read by the application, the new data overwrites the
data already waiting in AC97C_CxRHR, therefore the OVRUN flag in AC97C_CxSR is raised.
The application can either poll the OVRUN flag in AC97C_CxSR or wait for an interrupt notice.
The interrupt remains active until the OVRUN flag in AC97C_CxSR is set.
The AC’97 Controller can also be used in sound recording devices in association with an AC97
Codec. The AC‘97 Controller may also be exposed to heavy PCM transfers. The application can
use the PDC connected to channel A in order to reduce processor overhead and increase per-
formance especially under an operating system.
The PDC receive counter values must be equal to the number of PCM samples to be received,
each sample goes in one slot.
The AC’97 Controller receives a thirteen slot frame on the AC-Link sent by the AC97 Codec. The
first slot (tag slot or slot 0) flags the validity of the entire frame and the validity of each slot;
whether a slot carries valid data or not. Slots 1 and 2 are used if the application requires status
informations from AC97 Codec. Slots [3:12] are used according to AC’97 Controller Output
Channel Assignment Register (AC97C_ICA) content. The AC’97 Controller will not receive any
data from any slot if AC97C_ICA is not assigned to a channel in input.
Instead of polling flags in AC’97 Controller Global Status Register (AC97C_SR) and in AC’97
Controller Channel x Status Register (AC97C_CxSR), the application can wait for an interrupt
notice. The following steps show how to configure and use interrupts correctly:
The interrupt handler must read both AC’97 Controller Global Status Register (AC97C_SR) and
AC’97 Controller Interrupt Mask Register (AC97C_IMR) and AND them to get the real interrupt
source. Furthermore, to get which event was activated, the interrupt handler has to read AC’97
Controller Channel x Status Register (AC97C_CxSR), x being the channel whose event triggers
the interrupt.
STATUS
• Set the interruptible flag in AC’97 Controller Channel x Mode Register (AC97C_CxMR).
• Set the interruptible event and channel event in AC’97 Controller Interrupt Enable Register
ADDR
(AC97C_IER).
1
STATUS
DATA
2
LEFT
3
PCM
RIGHT
4
PCM
LINE 1
DAC
5
6
PCM
MIC
RSVED
7
RSVED
8
RSVED
9
LINE 2
ADC
10
6289C–ATARM–28-May-09
HSET
11
ADC
STATUS
12
IO