AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 727
AT91SAM9RL64-CU
Manufacturer Part Number
AT91SAM9RL64-CU
Description
IC ARM9 MCU 217-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9RL64-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, LCD, POR, PWM, WDT
Number Of I /o
118
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
72K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
2-Wire, SPI, SSC, USART
Maximum Clock Frequency
240 MHz
Number Of Programmable I/os
118
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Controller Family/series
AT91SAM9xxx
No. Of I/o's
118
Ram Memory Size
64KB
Cpu Speed
240MHz
No. Of Timers
1
Rohs Compliant
Yes
Package
217LFBGA
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
240 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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40.7.11
Register Name:
Access Type:
40.7.12
Register Name:
Access Type:
• CEM: Channel x Endian Mode
0: Transferring data through Channel x is straightforward (Little-endian).
1: Transferring data through Channel x from/to a memory is performed with from/to Big-endian format translation.
• SIZE: Channel x Data Size
SIZE Encoding
Note:
• CEN: Channel x Enable
0: Data transfer is disabled on Channel x.
1: Data transfer is enabled on Channel x.
6289C–ATARM–28-May-09
RXBUFF
31
23
15
31
23
15
–
–
7
–
–
–
–
7
–
Each time slot in the data phase is 20 bits long. For example, if a 16-bit sample stream is being played to an AC97 DAC, the first
16 bit positions are presented to the DAC MSB-justified. They are followed by the next four bit positions that the AC’97 Controller
fills with zeroes. This process ensures that the least significant bits do not introduce any DC biasing, regardless of the imple-
mented DAC’s resolution (16-, 18-, or 20-bit).
SIZE
AC’97 Controller Channel A Mode Register
AC’97 Controller Channel B Mode Register
0x0
0x1
0x2
0x3
ENDRX
PDCEN
30
22
14
30
22
14
AC97C_CAMR
Read/Write
–
6
–
AC97C_CBMR
Read/Write
–
–
–
6
–
Selected Channel
20 bits
18bits
16 bits
10 bits
OVRUN
OVRUN
CEN
CEN
29
21
13
29
21
13
–
–
5
–
–
5
RXRDY
RXRDY
28
20
12
28
20
12
–
–
–
4
–
–
–
4
AT91SAM9R64/RL64 Preliminary
TXBUFE
27
19
11
27
19
11
–
–
–
3
–
–
–
3
–
UNRUN
UNRUN
ENDTX
CEM
CEM
26
18
10
26
18
10
–
2
–
–
2
TXEMPTY
TXEMPTY
25
17
25
17
–
9
–
1
–
9
–
1
SIZE
SIZE
TXRDY
TXRDY
24
16
24
16
–
8
–
0
–
8
–
0
727
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