PIC18F66J15-I/PT Microchip Technology, PIC18F66J15-I/PT Datasheet - Page 406

• Manufacturer Part Number: PIC18F66J15-I/PT
• Description: IC PIC MCU FLASH 48KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F66J15-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 96KB (48K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J10 FAMILY
Timing Diagrams and Specifications
DS39663F-page 404
I
I
I
I
I
I
I
I
I
I
Master SSP I
Master SSP I
Parallel Slave Port (PSP) Read ............................... 150
Parallel Slave Port (PSP) Write ............................... 149
Program Memory Read ............................................ 368
Program Memory Write ............................................ 369
PWM Auto-Shutdown (P1RSEN = 0,
PWM Auto-Shutdown (P1RSEN = 1,
PWM Direction Change ........................................... 187
PWM Direction Change at Near
PWM Output ............................................................ 174
Repeated Start Condition ......................................... 228
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................ 254
Slave Synchronization ............................................. 199
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 198
SPI Mode (Slave Mode, CKE = 0) ........................... 200
SPI Mode (Slave Mode, CKE = 1) ........................... 200
Synchronous Reception (Master Mode, SREN) ...... 257
Synchronous Transmission ...................................... 255
Synchronous Transmission (Through TXEN) .......... 256
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 371
Transition for Entry to Idle Mode ................................ 44
Transition for Entry to SEC_RUN Mode .................... 41
Transition for Entry to Sleep Mode ............................ 43
Transition for Two-Speed Start-up
Transition for Wake From Idle to Run Mode .............. 44
Transition for Wake From Sleep (HSPLL) ................. 43
Transition From RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 42
AC Characteristics
2
2
2
2
2
2
2
2
2
2
C Slave Mode (10-Bit Reception, SEN = 0,
C Slave Mode (10-Bit Reception, SEN = 0) .......... 216
C Slave Mode (10-Bit Reception, SEN = 1) .......... 221
C Slave Mode (10-Bit Transmission) ..................... 217
C Slave Mode (7-Bit Reception, SEN = 0,
C Slave Mode (7-Bit Reception, SEN = 0) ............ 212
C Slave Mode (7-Bit Reception, SEN = 1) ............ 220
C Slave Mode (7-Bit Transmission) ....................... 214
C Slave Mode General Call Address Sequence
C Stop Condition Receive or Transmit Mode ........ 232
ADMSK = 01001) ............................................. 215
ADMSK = 01011) ............................................. 213
(7 or 10-Bit Addressing Mode) ......................... 222
Auto-Restart Disabled) ..................................... 190
Auto-Restart Enabled) ..................................... 190
100% Duty Cycle ............................................. 187
Timer (OST) and Power-up Timer (PWRT) ..... 370
V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTRC to HSPLL) ........................................... 289
PRI_RUN Mode ................................................. 42
PRI_RUN Mode (HSPLL) .................................. 41
Internal RC Accuracy ....................................... 365
DD
Rise > T
2
2
C Bus Data ........................................ 379
C Bus Start/Stop Bits ........................ 379
PWRT
DD
) ............................................ 51
, V
DD
DD
DD
), Case 1 ....................... 50
), Case 2 ....................... 51
Rise < T
DD
,
PWRT
) ........... 50
Top-of-Stack Access .......................................................... 63
TRISE Register
TSTFSZ ........................................................................... 333
Two-Speed Start-up ................................................. 281, 289
Two-Word Instructions
TXSTAx Register
U
Unused I/Os ....................................................................... 30
V
V
Voltage Reference Specifications .................................... 361
Voltage Regulator (On-Chip) ........................................... 288
W
Watchdog Timer (WDT) ........................................... 281, 287
WCOL ...................................................... 227, 228, 229, 232
WCOL Status Flag ................................... 227, 228, 229, 232
WWW Address ................................................................ 405
WWW, On-Line Support ...................................................... 4
X
XORLW ............................................................................ 333
XORWF ........................................................................... 334
DDCORE
Capture/Compare/PWM Requirements
CLKO and I/O Requirements ........................... 366, 368
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode Requirements
External Clock Requirements .................................. 364
I
I
Master SSP I
Master SSP I
Parallel Slave Port Requirements ............................ 372
PLL Clock ................................................................ 365
Program Memory Write Requirements .................... 369
Reset, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External Clock
PSPMODE Bit .......................................................... 148
Example Cases .......................................................... 67
BRGH Bit ................................................................. 243
Associated Registers ............................................... 287
Control Register ....................................................... 287
During Oscillator Failure .......................................... 290
Programming Considerations .................................. 287
2
2
C Bus Data Requirements (Slave Mode) .............. 378
C Bus Start/Stop Bits Requirements
/V
(Including ECCP Modules) .............................. 372
Requirements .................................................. 381
Requirements .................................................. 381
(Master Mode, CKE = 0) .................................. 373
(Master Mode, CKE = 1) .................................. 374
(Slave Mode, CKE = 0) .................................... 375
(CKE = 1) ......................................................... 376
(Slave Mode) ................................................... 377
Requirements .................................................. 379
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 370
Requirements .................................................. 371
CAP
Pin .......................................................... 288
2
2
C Bus Data Requirements ................ 380
C Bus Start/Stop Bits
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