PIC18F66J15-I/PT Microchip Technology, PIC18F66J15-I/PT Datasheet
PIC18F66J15-I/PT
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PIC18F66J15-I/PT Summary of contents
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... Microchip Technology Inc. PIC18F87J10 Family 64/80-Pin, High-Performance 1-Mbit Flash Microcontrollers with nanoWatt Technology Data Sheet DS39663F ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Internal 31 kHz Oscillator • Secondary Oscillator using Timer1 @ 32 kHz • Two-Speed Oscillator Start-up • Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock stops © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Peripheral Highlights: • High-Current Sink/Source 25 mA/25 mA (PORTB and PORTC) • ...
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... PIC18F87J10 FAMILY Program Memory SRAM Data Device Flash # Single-Word (bytes) Instructions PIC18F65J10 32K 16384 PIC18F65J15 48K 24576 PIC18F66J10 64K 32768 PIC18F66J15 96K 49152 PIC18F67J10 128K 65536 PIC18F85J10 32K 16384 PIC18F85J15 48K 24576 PIC18F86J10 64K 32768 PIC18F86J15 96K 49152 PIC18F87J10 128K 65536 ...
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... RH7/AN15/P1B 19 (2) RH6/AN14/P1C 20 Note 1: The ECCP2/P2A pin placement depends on the setting of the CCP2MX Configuration bit and the program memory mode. 2: P1B, P1C, P3B and P3C pin placement depends on the setting of the ECCPMX Configuration bit. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39663F-page 4 © 2009 Microchip Technology Inc. ...
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... PIC18F65J10 • PIC18F85J10 • PIC18F65J15 • PIC18F85J15 • PIC18F66J10 • PIC18F86J10 • PIC18F66J15 • PIC18F86J15 • PIC18F67J10 • PIC18F87J10 This family introduces a new line of low-voltage devices with the main traditional advantage of all PIC18 micro- controllers – namely, high computational performance and a rich feature set – ...
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... I/O ports (7 bidirectional ports on 64-pin devices, 9 bidirectional ports on 80-pin devices). All other features for devices in this family are identical. These are summarized in Table 1-1 and Table 1-2. The pinouts for all devices are listed in Table 1-3 and Table 1-4. © 2009 Microchip Technology Inc. devices to for ...
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... MSSP (2), Enhanced USART (2) Yes 15 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set enabled 80-pin TQFP PIC18F66J15 PIC18F67J10 DC – 40 MHz DC – 40 MHz 96K 128K 49152 65536 3936 3936 DC – 40 MHz DC – ...
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... Timer BITOP Reset ALU<8> Timer (2) Reset MCLR SS Timer1 Timer2 Timer3 Timer4 CCP4 CCP5 EUSART1 EUSART2 PORTA (1) RA0:RA5 12 PORTB (1) RB0:RB7 4 Access Bank 12 PORTC (1) RC0:RC7 PORTD (1) RD0:RD7 8 PRODL PORTE (1) RE0:RE7 PORTF 8 (1) RF1:RF7 8 PORTG (1) RG0:RG4 Comparators MSSP1 MSSP2 © 2009 Microchip Technology Inc. ...
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... ADC Timer0 10-Bit ECCP1 ECCP2 ECCP3 Note 1: See Table 1-4 for I/O port pin descriptions. 2: BOR functionality is provided when the on-board voltage regulator is enabled. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Data Latch 8 8 Data Memory (2.0, 3.9 Kbytes) PCLATH PCLATU ...
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... Analog input 3. I Analog A/D reference voltage (high) input. I/O ST Digital I/ Timer0 external clock input. I/O TTL Digital I/O. I Analog Analog input 4. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... C/SMB = I C™/SMBus input buffer Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs ...
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... I/O ST EUSART1 synchronous clock (see related RX1/DT1). I/O ST Digital I/ EUSART1 asynchronous receive. I/O ST EUSART1 synchronous data (see related TX1/CK1). CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description 2 C™ mode © 2009 Microchip Technology Inc. ...
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... C/SMB = I C™/SMBus input buffer Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Pin Buffer Type Type PORTD is a bidirectional I/O port. ...
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... ECCP1 PWM output C. I/O ST Digital I/O. O — ECCP1 PWM output B. I/O ST Digital I/O. I/O ST Capture 2 input/Compare 2 output/PWM 2 output. O — ECCP2 PWM output A. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... C/SMB = I C™/SMBus input buffer Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Pin Buffer Type Type PORTF is a bidirectional I/O port. ...
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... Core logic power or external filter capacitor connection. P — Positive supply for microcontroller core logic (regulator disabled). P — External filter capacitor connection (regulator enabled). CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Pin Buffer Type Type I ST Master Clear (Reset) input ...
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... In-Circuit Debugger and ICSP™ programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP™ programming data pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. ...
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... Synchronous serial clock input/output for I I/O ST Digital I/O. I/O TTL External memory address/data 7. I/O TTL Parallel Slave Port data. I TTL SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description 2 C mode © 2009 Microchip Technology Inc. ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Pin Buffer Type Type PORTE is a bidirectional I/O port. ...
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... Analog input 10. O — Comparator reference voltage output. I/O ST Digital I/O. I Analog Analog input 11. I/O ST Digital I/O. I TTL SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Pin Buffer Type Type PORTG is a bidirectional I/O port. ...
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... I/O ST Digital I/O. I Analog Analog input 14. O — ECCP1 PWM output C. I/O ST Digital I/O. I Analog Analog input 15. O — ECCP1 PWM output B. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Pin Buffer Type Type PORTJ is a bidirectional I/O port. ...
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... PIC18F87J10 FAMILY NOTES: DS39663F-page 26 © 2009 Microchip Technology Inc. ...
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... REF reference for analog modules is implemented Note: The AV and AV pins must always connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY FIGURE 2- MCLR C1 V (2) C6 ...
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... The DD may be beneficial. A typical ) and fast signal transitions must IL is replaced for normal run-time EXAMPLE OF MCLR PIN CONNECTIONS R1 R2 MCLR PIC18FXXJXX JP C1 and V specifications are met and V specifications are met. IL © 2009 Microchip Technology Inc. ...
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... Frequency (MHz) Note: Data for Murata GRM21BF50J106ZE01 shown. Measurements at 25° bias. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 2.5 ICSP Pins The PGC and PGD pins are used for In-Circuit Serial Programming (ICSP) and debugging purposes recommended to keep the trace length between the ...
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... Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 kΩ kΩ resistor to V output to logic low. Devices” SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT unused pins and drive the SS © 2009 Microchip Technology Inc. ...
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... The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a fre- quency out of the crystal manufacturer’s specifications. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY FIGURE 3-1: ( Output (1) C2 Note 1: See Table 3-1 and Table 3-2 for initial values of C1 and C2 ...
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... OSC1 pin in the HS mode, as shown in Figure 3-3. In this configuration, the divide-by-4 output on OSC2 is not available. FIGURE 3-3: Clock from of external Ext. System EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18F87J10 OSC2/CLKO /4 OSC EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 PIC18F87J10 (HS Mode) Open OSC2 © 2009 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ Note 1: Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and read as ‘0’. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY FIGURE 3-4: PLL BLOCK DIAGRAM HSPLL or ECPLL (CONFIG2L) PLL Enable (OSCTUNE) ...
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... Features of the CPU” for Configuration register details. PIC18F87J10 Family HS, EC HSPLL, ECPLL 4 x PLL T1OSC Internal Oscillator INTRC Source FOSC<2:0> Clock Source Option for Other Modules WDT, PWRT, FSCM and Two-Speed Start-up © 2009 Microchip Technology Inc. Peripherals CPU IDLEN Clock Control OSCCON<1:0> ...
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... It is recommended that the Timer1 oscillator be operating and stable before executing the SLEEP instruction or a very long delay may occur while the Timer1 oscillator starts. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 3.6.1.1 System Clock Selection and the FOSC2 Configuration Bit The SCS bits are cleared on all forms of Reset. In the device’ ...
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... The Reset value is ‘0’ when HS mode and Two-Speed Start-up are both enabled; otherwise ‘1’. DS39663F-page 36 (1) U-0 R-q U-0 — OSTS — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) © 2009 Microchip Technology Inc. R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown ...
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... Feedback inverter disabled at quiescent voltage level Note: See Table 5-2 in Section 5.0 “Reset” for time-outs due to Sleep and MCLR Reset. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Timer1 oscillator may be operating to support a Real-Time Clock. Other features may be operating that do not require a device clock source (i.e., MSSP slave, PSP, INTx pins and others) ...
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... PIC18F87J10 FAMILY NOTES: DS39663F-page 38 © 2009 Microchip Technology Inc. ...
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... RC_IDLE 1 11 Note 1: IDLEN reflects its value when the SLEEP instruction is executed. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 4.1.1 CLOCK SOURCES The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: • The primary clock, as defined by the FOSC<2:0> ...
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... SEC_RUN mode is entered by setting the SCS<1:0> bits to ‘01’. The device clock source is switched to the Timer1 oscillator (see Figure 4-1), the primary oscilla- tor is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. © 2009 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. OST OSC PLL © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY On transitions from SEC_RUN mode to PRI_RUN, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 4-2) ...
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... The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n Clock Transition (1) (1) T PLL 1 2 n-1 n Clock Transition OSTS Bit Set © 2009 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. OST OSC PLL © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 4.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘ ...
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... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result CSD © 2009 Microchip Technology Inc. ...
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... Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 4.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs ...
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... PIC18F87J10 FAMILY NOTES: DS39663F-page 46 © 2009 Microchip Technology Inc. ...
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... INTRC 11-Bit Ripple Counter Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip voltage regulator when there is insufficient source voltage to maintain regulation. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 5.1 RCON Register Device Reset events are tracked through the RCON register (Register ) ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset. DS39663F-page 48 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 POR BOR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... BOR running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once V rises above V , the Power-up Timer will execute the BOR additional time delay. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY FIGURE 5- Note 1: External Power-on Reset circuit is required ...
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... PWRT will expire. Bringing MCLR high will begin (Figure 5-5). This is useful for testing purposes synchronize more than one PIC18FXXXX device operating in parallel PWRT T PWRT © 2009 Microchip Technology Inc. all depict time-out execution immediately , V RISE < PWRT ): CASE 1 DD ...
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... FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY T PWRT , V RISE > 3. PWRT ): CASE ...
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... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register ( 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h STKPTR Register POR BOR STKFUL STKUNF © 2009 Microchip Technology Inc. ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset ...
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... Microchip Technology Inc. ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset ...
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... Microchip Technology Inc. ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset ...
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... PIC18F87J10 FAMILY NOTES: DS39663F-page 58 © 2009 Microchip Technology Inc. ...
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... Unimplemented Read as ‘0’ Read as ‘0’ Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 6.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter which is capable of addressing a 2-Mbyte program memory space ...
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... WORD FOR PIC18F87J10 FAMILY DEVICES Program Configuration Device Memory (Kbytes) PIC18F65J10 32 7FF8h to 7FFFh PIC18F85J10 PIC18F65J15 48 BFF8h to BFFFh PIC18F85J15 PIC18F66J10 64 FFF8h to FFFFh PIC18F86J10 PIC18F66J15 96 PIC18F86J15 PIC18F67J10 128 PIC18F87J10 © 2009 Microchip Technology Inc. through Word Addresses 17FF8h to to 17FFFh 1FFF8h to to 1FFFFh ...
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... Address shifting enabled – external address bus is shifted to start at 000000h 0 = Address shifting disabled – external address bus reflects the PC value bit 2-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY • The Extended Microcontroller Mode allows access to both internal and external program memories as a single block. The device can access its entire on-chip program memory ...
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... Yes Yes Yes (2) with Address Shifting On-Chip Memory Space 000000h On-Chip Program Memory (Top of Memory) (Top of Memory Mapped to External Memory 1FFFFFh – Space (Top of Memory) 1FFFFFh Table Read Table Write From To No Access No Access Yes Yes © 2009 Microchip Technology Inc. ...
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... TOSH TOSL 00h 1Ah 34h © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers ...
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... Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. R/W-0 R/W-0 R/W-0 SP4 SP3 SP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) R/W-0 R/W-0 SP1 SP0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... SUB1 • RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 6.1.8 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
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... Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write Execute INST (PC) Execute INST ( Fetch INST ( Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch Internal Phase Clock Fetch INST ( Flush (NOP) Fetch SUB_1 Execute SUB_1 © 2009 Microchip Technology Inc. ...
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... MOVFF 1111 0100 0101 0110 0010 0100 0000 0000 ADDWF © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...
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... This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. © 2009 Microchip Technology Inc. ...
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... Bank 6 FFh 00h = 0111 Bank 7 FFh 00h = 1000 Bank 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Data Memory Map 000h Access RAM 05Fh 060h GPR 0FFh 100h GPR 1FFh 200h GPR 2FFh 300h GPR ...
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... RAM (from Bank 0). The remaining 160 bytes are Special Function Registers (from Bank 15). When The BSR specifies the bank used by the instruction. Access Bank 00h Access RAM Low 5Fh 60h Access RAM High (SFRs) FFh © 2009 Microchip Technology Inc. ...
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... BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Data Memory 000h 7 ...
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... LATC F6Bh RCSTA2 LATB F6Ah ECCP3AS LATA F69h ECCP3DEL (3) PORTJ F68h ECCP2AS (3) PORTH F67h ECCP2DEL PORTG F66h SSP2BUF PORTF F65h SSP2ADD PORTE F64h SSP2STAT PORTD F63h SSP2CON1 PORTC F62h SSP2CON2 (2) PORTB F61h — (2) PORTA F60h — © 2009 Microchip Technology Inc. ...
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... The PLLEN bit is available only when either ECPLL or HSPLL Oscillator modes are selected; otherwise, the bit is read as ‘0’. 5: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Bit 4 Bit 3 Bit 2 — ...
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... PSS1BD0 55, 189 0000 0000 CVR0 55, 277 0000 0000 CM0 55, 271 0000 0111 55, 165 xxxx xxxx 55, 165 xxxx xxxx TMR3ON 55, 163 0000 0000 — 55, 149 0000 ---- 0000 0000 55, 243 55, 251, 0000 0000 252 © 2009 Microchip Technology Inc. ...
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... The PLLEN bit is available only when either ECPLL or HSPLL Oscillator modes are selected; otherwise, the bit is read as ‘0’. 5: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Bit 4 Bit 3 Bit 2 ...
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... P3DC0 57, 188 0000 0000 PSS2BD0 57, 189 0000 0000 P2DC0 0000 0000 57, 188 57, 203, xxxx xxxx 238 57, 203 0000 0000 BF 57, 194, 0000 0000 204 SSPM0 57, 206, 0000 0000 205 SEN 57, 206 0000 0000 © 2009 Microchip Technology Inc. ...
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... For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY register then reads back as ‘000u u1uu’ recom- ...
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... EXAMPLE 6-5: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING LFSR FSR0, 100h ; NEXT CLRF POSTINC0 ; Clear INDF ; register then ; inc pointer BTFSS FSR0H All done with ; Bank1? BRA NEXT ; NO, clear next CONTINUE ; YES, continue © 2009 Microchip Technology Inc. Stack Pointer ...
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... FCCh. This means the contents of location FCCh will be added to that of the W register and stored back in FCCh. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L ...
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... Indirect Addressing. Similarly, operations by Indirect Addressing are gener- ally permitted on all other SFRs. Users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device. © 2009 Microchip Technology Inc. ...
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... Indexed Addressing using an offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal Offset, or Indexed Literal Offset mode. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY When using the extended instruction set, this addressing mode requires the following: • ...
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... FSR2H F00h Bank 15 F60h SFRs FFFh Data Memory BSR 000h 00000000 Bank 0 060h 100h 001001da Bank 1 through Bank 14 F00h Bank 15 F60h SFRs FFFh Data Memory © 2009 Microchip Technology Inc. 00h 60h Valid range for ‘f’ FFh ffffffff FSR2L ffffffff ...
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... F00h BSR. F60h FFFh © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. Any Indirect or ...
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... PIC18F87J10 FAMILY NOTES: DS39663F-page 84 © 2009 Microchip Technology Inc. ...
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... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: The Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 7.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... Reset write operation was attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Reading Table Latch (8-bit) TABLAT © 2009 Microchip Technology Inc. ...
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... Initiates a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once the write is complete. The WR bit can only be set (not cleared) in software Write cycle is complete bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY R/W-0 R/W-x R/W-0 FREE ...
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... Figure 7-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TABLE READ: TBLPTR<21:0> TBLPTRL 0 © 2009 Microchip Technology Inc. ...
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... WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVF WORD_ODD © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
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... The CPU will stall for duration of the erase for T (see parameter D133B Re-enable interrupts. ; load TBLPTR with the base ; address of the memory block ; enable write to memory ; enable Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts © 2009 Microchip Technology Inc. ...
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... Write the 64 bytes into the holding registers with auto-increment. 7. Set the WREN bit (EECON1<2>) to enable byte writes. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device ...
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... TBLWT holding register. ; loop until buffers are full ; enable write to memory ; disable interrupts ; write 55h ; write 0AAh ; start program (CPU stall) ; re-enable interrupts ; disable write to memory ; done with one write cycle ; if not done replacing the erase block © 2009 Microchip Technology Inc. ...
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... EECON2 Program Memory Control Register 2 (not a physical register) EECON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during program memory access. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 7.6 Flash Program Operation During Code Protection See Section 24.6 “Program Verification and Code Protection” ...
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... PIC18F87J10 FAMILY NOTES: DS39663F-page 94 © 2009 Microchip Technology Inc. ...
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... Note: For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional multiplexed features may be available on some pins. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY The bus is implemented with 28 pins, multiplexed across four I/O ports. Three ports (PORTD, PORTE ...
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... Data Width Modes”. These bits have no effect when an 8-Bit Data Width mode is selected. R/W-0 U-0 U-0 WAIT0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 WM1 WM0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F87J10 FAMILY 8.2.1 ADDRESS SHIFTING ON THE EXTERNAL BUS By default, the address presented on the external bus is the value of the PC. In practical terms, this means that addresses in the external memory device below the top of on-chip memory are unavailable to the micro- controller ...
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... BA0 for the byte address line and one I/O line to select between Byte and Word mode. The other 16-bit modes do not need BA0. JEDEC standard static RAM memories will use the signals for byte selection. © 2009 Microchip Technology Inc. register ...
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... Upper order address lines are used only for 20-bit address widths. 2: This signal only applies to table writes. See Section 7.1 “Table Reads and Table Writes”. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the AD< ...
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... The obvious limitation to this method is that the even address table write must be done in pairs on a specific word boundary to correctly write a word location. A<20:1> 373 D<15:0> 373 cycle to an odd address JEDEC Word A<x:0> EPROM Memory D<15:0> ( Address Bus Data Bus Control Lines © 2009 Microchip Technology Inc. ...
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... Upper order address lines are used only for 20-bit address width. 3: Demultiplexing is only required when multiple memory devices are accessed. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory’ ...
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... Opcode Fetch TBLRD 92h MOVLW 55h from 199E67h from 000102h TBLRD Cycle 1 TBLRD Cycle 00h 0E55h 3AABh Opcode Fetch Sleep Mode, MOVLW 55h from 007556h SLEEP Opcode Fetch ADDLW 55h from 000104h MOVLW Bus Inactive © 2009 Microchip Technology Inc. ...
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... This signal only applies to table writes. See Section 7.1 “Table Reads and Table Writes”. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the second byte will be enabled to form the 16-bit instruc- tion word ...
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... Opcode Fetch TBLRD 92h MOVLW 55h from 199E67h from 000102h TBLRD Cycle 1 TBLRD Cycle 00h 3Ah 0Eh 55h ABh Opcode Fetch Sleep Mode, MOVLW 55h from 007556h SLEEP Opcode Fetch ADDLW 55h from 000104h MOVLW Bus Inactive © 2009 Microchip Technology Inc. ...
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... If operations in a lower power Run mode are anticipated, users should provide in their applications for adjusting memory access times at the lower clock speeds. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY In Sleep and Idle modes, the microcontroller core does not need to access data; bus operations are suspended ...
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... PIC18F87J10 FAMILY NOTES: DS39663F-page 106 © 2009 Microchip Technology Inc. ...
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... Without Hardware Multiply unsigned Hardware Multiply Without Hardware Multiply signed Hardware Multiply Without Hardware Multiply unsigned Hardware Multiply Without Hardware Multiply signed Hardware Multiply © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY EXAMPLE 9- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...
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... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H © 2009 Microchip Technology Inc. ...
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... Individual interrupts can be disabled through their corresponding enable bits. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...
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... IPEN PEIE/GIEL IPEN TMR0IF IPEN TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP © 2009 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL ...
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... None of the RB<7:4> pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Note: Interrupt flag bits are set when an interrupt ...
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... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39663F-page 112 R/W-1 R/W-1 R/W-1 INTEDG2 INTEDG3 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY R/W-0 ...
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... R-0 R/W-0 R/W-0 TX1IF SSP1IF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... A TMR1/TMR3 register capture occurred (must be cleared in software TMR1/TMR3 register capture occurred Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1 or TMR3 register compare match occurred PWM mode: Unused in this mode. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY U-0 R/W-0 U-0 — BCL1IF — ...
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... A TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. DS39663F-page 116 R-0 R/W-0 R/W-0 TX2IF TMR4IF CCP5IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 CCP4IF CCP3IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY R/W-0 R/W-0 R/W-0 TX1IE SSP1IE CCP1IE U = Unimplemented bit, read as ‘ ...
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... TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: ECCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS39663F-page 118 U-0 R/W-0 U-0 — BCL1IE — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. R/W-0 R/W-0 TMR3IE CCP2IE bit Bit is unknown ...
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... Enabled 0 = Disabled bit 1 CCP4IE: CCP4 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP3IE: ECCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY R-0 R/W-0 R/W-0 TX2IE TMR4IE CCP5IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 ...
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... Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS39663F-page 120 R/W-1 R/W-1 R/W-1 TX1IP SSP1IP CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY U-0 R/W-1 U-0 — BCL1IP — Unimplemented bit, read as ‘0’ ...
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... Low priority bit 0 CCP3IP: ECCP3 Interrupt Priority bit 1 = High priority 0 = Low priority DS39663F-page 122 R/W-1 R/W-1 R/W-1 TX2IP TMR4IP CCP5IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 CCP4IP CCP3IP bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... For details of bit operation, see Register 4-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-1. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY R/W-1 R-1 R Unimplemented bit, read as ‘ ...
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... Example 10-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS © 2009 Microchip Technology Inc. ...
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... TRIS Latch RD TRIS Port © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 11.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 11 ...
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... MOVWF TRISA + and REF INITIALIZING PORTA ; Initialize PORTA by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Configure A/D ; Configure comparators ; for digital input ; Value used to ; initialize data ; direction ; Set RA<3:0> as inputs ; RA<5:4> as outputs © 2009 Microchip Technology Inc. ...
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... LATA — — TRISA — — ADCON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY I/O I/O Type O DIG LATA<0> data output; not affected by analog input. I TTL PORTA<0> data input; disabled when analog input enabled. ...
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... Configuration bit. This applies only to 80-pin devices operating in Extended Microcontroller mode. If the device is in Microcontroller mode, the alternate assignment for ECCP2 is RE7. As with other ECCP2 configurations, the user must ensure that the TRISB<3> bit is set appropriately for the intended operation. © 2009 Microchip Technology Inc. device from ...
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... Note 1: Alternate assignment for ECCP2/P2A when the CCP2MX Configuration bit is cleared (Extended Microcontroller mode, 80-pin devices only); default assignment is RC1. 2: All other pin functions are disabled when ICSP or ICD are enabled. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY I/O I/O Type ...
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... RB5 RB4 RB3 RB2 LATB5 LATB4 LATB3 LATB2 TRISB5 TRISB4 TRISB3 TRISB2 INT0IE RBIE TMR0IF INT3IE INT2IE INT1IE INT3IF Reset Bit 1 Bit 0 Values on page RB1 RB0 56 LATB1 LATB0 56 TRISB1 TRISB0 56 INT0IF RBIF 53 INT3IP RBIP 53 INT2IF INT1IF 53 © 2009 Microchip Technology Inc. ...
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... TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Note: These pins are configured as digital inputs on any device Reset ...
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... Asynchronous serial receive data input (EUSART1 module). DIG Synchronous serial data output (EUSART1 module); takes priority over port data. ST Synchronous serial data input (EUSART1 module). User must configure as an input C™/SMB = I C/SMBus input buffer, ANA = Analog Signal, DIG = Digital Out- Description © 2009 Microchip Technology Inc. ...
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... TABLE 11-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC LATC7 LATBC6 TRISC TRISC7 TRISC6 © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 LATC5 LATCB4 LATC3 LATC2 TRISC5 TRISC4 TRISC3 ...
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... EXAMPLE 11-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs © 2009 Microchip Technology Inc. ...
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... Output Schmitt Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: External memory interface I/O takes priority over all other digital and PSP I/O. 2: Available on 80-pin devices only. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY I/O I/O Type O DIG LATD< ...
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... Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 RD2 LATD5 LATD4 LATD3 LATD2 TRISD5 TRISD4 TRISD3 TRISD2 (1) RJPU RG4 RG3 RG2 Description (1) (1) (1) (1) Reset Bit 1 Bit 0 Values on page RD1 RD0 56 LATD1 LATD0 56 TRISD1 TRISD0 56 RG1 RG0 56 © 2009 Microchip Technology Inc. ...
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... REPU (PORTG<6>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on any device Reset. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY PORTE is also multiplexed with Enhanced PWM outputs B and C for ECCP1 and ECCP3 and outputs B, C and D for ECCP2. For all devices, their default assignments are on PORTE< ...
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... TTL External memory interface, data bit 13 input. O DIG ECCP1 Enhanced PWM output, Channel C; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. Description (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) © 2009 Microchip Technology Inc. ...
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... LATE LATE7 LATE6 TRISE TRISE7 TRISE6 PORTG RDPU REPU Legend: Shaded cells are not used by PORTE. Note 1: Unimplemented on 64-pin devices, read as ‘0’. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY I/O I/O Type O DIG LATE<6> data output PORTE<6> data input. O DIG External memory interface, address/data bit 14 output ...
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... MOVLW 07h ; MOVWF CMCON ; Turn off comparators MOVLW 0Fh; MOVWF ADCON1 ; Set PORTF as digital I/O MOVLW 0CEh ; Value used to ; initialize data ; direction MOVWF TRISF ; Set RF3:RF1 as inputs ; RF5:RF4 as outputs ; RF7:RF6 as inputs © 2009 Microchip Technology Inc. ...
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... ADCON1 — — CMCON C2OUT C1OUT CVRCON CVREN CVROE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY I/O I/O Type O DIG LATF<1> data output; not affected by analog input PORTF<1> data input; disabled when analog input enabled. ...
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... EXAMPLE 11-7: INITIALIZING PORTG CLRF PORTG ; Initialize PORTG by ; clearing output ; data latches CLRF LATG ; Alternate method ; to clear output ; data latches MOVLW 04h ; Value used to ; initialize data ; direction MOVWF TRISG ; Set RG1:RG0 as outputs ; RG2 as input ; RG4:RG3 as inputs © 2009 Microchip Technology Inc. ...
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... LATG — — TRISG — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG. Note 1: Unimplemented on 64-pin devices, read as ‘0’. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY I/O Type DIG LATG<0> data output PORTG<0> data input. ...
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... CLRF LATH ; Alternate method ; to clear output ; data latches MOVLW 0Fh ; Configure PORTH as MOVWF ADCON1 ; digital I/O MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISH ; Set RH3:RH0 as inputs ; RH5:RH4 as outputs ; RH7:RH6 as inputs © 2009 Microchip Technology Inc. ...
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... Bit 7 Bit 6 PORTH RH7 RH6 LATH LATH7 LATH6 TRISH TRISH7 TRISH6 © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY I/O Type DIG LATH<0> data output. ST PORTH<0> data input. DIG External memory interface, address line 16. Takes priority over port data. DIG LATH<1> data output. ...
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... EXAMPLE 11-9: INITIALIZING PORTJ CLRF PORTJ ; Initialize PORTG by ; clearing output ; data latches CLRF LATJ ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISJ ; Set RJ3:RJ0 as inputs ; RJ5:RJ4 as output ; RJ7:RJ6 as inputs © 2009 Microchip Technology Inc. ...
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... RJ7 RJ6 LATJ LATJ7 LATJ6 TRISJ TRISJ7 TRISJ6 TRISJ5 PORTG RDPU REPU Legend: Shaded cells are not used by PORTJ. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY I/O I/O Type O DIG LATJ<0> data output PORTJ<0> data input. O DIG External memory interface address latch enable control output; takes priority over digital I/O ...
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... Q WR LATD CK or PORTD Data Latch PORTD EN EN TRIS Latch RD LATD One bit of PORTD Set Interrupt Flag PSPIF (PIR1<7>) Read Chip Select Write Note: I/O pin has protection diodes © 2009 Microchip Technology Inc. RDx Pin TTL RD TTL CS TTL WR TTL and ...
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... General Purpose I/O mode bit 3-0 Unimplemented: Read as ‘0’ FIGURE 11-3: PARALLEL SLAVE PORT WRITE WAVEFORMS PORTD<7:0> IBF OBF PSPIF © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY R/W-0 U-0 PSPMODE — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 ...
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... RC1IE TX1IE SSP1IE CCP1IE RC1IP TX1IP SSP1IP CCP1IP Reset Bit 1 Bit 0 Values on page RD1 RD0 56 LATD1 LATD0 56 TRISD1 TRISD0 56 RE1 RE0 56 LATE1 LATE0 56 TRISE1 TRISE0 56 — — — 55 INT0IF RBIF 53 TMR2IF TMR1IF 55 TMR2IE TMR1IE 55 TMR2IP TMR1IP 55 © 2009 Microchip Technology Inc. ...
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... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 12-1 ...
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... Sync with Internal TMR0L Clocks Delay There is a delay between OSC Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
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... TMR0ON T08BIT TRISA — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 12.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution ...
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... PIC18F87J10 FAMILY NOTES: DS39663F-page 154 © 2009 Microchip Technology Inc. ...
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... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY A simplified block diagram of the Timer1 module is shown in Figure 13-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 13-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
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... Special Event Trigger Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR1H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
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... TIMER1 LP OSCILLATOR C1 PIC18F87J10 27 pF T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 13-1 for additional information about capacitor selection. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY TABLE 13-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Oscillator Freq. C1 Type ( kHz 27 pF ...
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... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. © 2009 Microchip Technology Inc. ...
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... Timer1 Register High Byte T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: Shaded cells are not used by the Timer1 module. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ...
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... PIC18F87J10 FAMILY NOTES: DS39663F-page 160 © 2009 Microchip Technology Inc. ...
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... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 14.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
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... Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TX1IF SSP1IF CCP1IF TX1IE SSP1IE CCP1IE TX1IP SSP1IP CCP1IP Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 53 TMR2IF TMR1IF 55 TMR2IE TMR1IE 55 TMR2IP TMR1IP © 2009 Microchip Technology Inc. ...
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... OSC bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY A simplified block diagram of the Timer3 module is shown in Figure 15-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 15-2. The Timer3 module is controlled through the T3CON register (Register 15-1). It also selects the clock source options for the CCP and ECCP modules ...
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... RC1/T1OSI and 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR3H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
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... T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 15.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
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... PIC18F87J10 FAMILY NOTES: DS39663F-page 166 © 2009 Microchip Technology Inc. ...
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... Timer4 is off bit 1-0 T4CKPS<1:0>: Timer4 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 16.1 Timer4 Operation Timer4 can be used as the PWM time base for the PWM mode of the CCP module. The TMR4 register is readable and writable and is cleared on any device Reset ...
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... Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TX2IP TMR4IP CCP5IP TX2IF TMR4IF CCP5IF TX2IE TMR4IE CCP5IE Set TMR4IF TMR4 Output (to PWM) PR4 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 53 CCP4IP CCP3IP 55 CCP4IF CCP3IF 55 CCP4IE CCP3IE © 2009 Microchip Technology Inc. ...
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... Compare mode; generate software interrupt on compare match (CCPxIF bit is set, CCPx pin reflects I/O state) 1011 = Reserved 11xx = PWM mode © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY register. For the sake of clarity, all CCP module opera- tion in the following sections is described with respect to CCP4, but is equally applicable to CCP5 ...
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... CCP modules. Timer4 is used for PWM operations for all CCP modules. Modules may share either timer resource as a common time base. or PWM Timer1 and Timer2 are not available. timer are in or PWM © 2009 Microchip Technology Inc. ...
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... CCP4CON<3:0> Q1:Q4 CCP5CON<3:0> CCP5 pin Prescaler ÷ © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 17.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode ...
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... Only a CCP interrupt is generated, if enabled and the CCPxIE bit is set. Set CCP4IF Compare Output Match Logic 4 CCP4CON<3:0> T3CCP2 Set CCP5IF Compare Output Match Logic 4 CCP5CON<3:0> CCP4 Pin TRIS Output Enable CCP5 Pin TRIS Output Enable © 2009 Microchip Technology Inc. ...
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... Capture/Compare/PWM Register 5 Low Byte CCPR5H Capture/Compare/PWM Register 5 High Byte CCP4CON — — CCP5CON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by capture/compare, Timer1 or Timer3. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — ...
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... CCPRxH until after a match between PR2 (PR4) and TMR2 (TMR4) occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. • OSC (TMR2 Prescale Value) “Timer2 Module” and L:CCP CON<5:4>) • • (TMR2 Prescale Value) OSC © 2009 Microchip Technology Inc. ...
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... EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz Timer Prescaler (1, 4, 16) PR2 Value FFh Maximum Resolution (bits) © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 17.4.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. ...
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... DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 Reset Bit 2 Bit 1 Bit 0 Values on page INT0IF RBIF 53 PD POR BOR 54 TMR2IF TMR1IF 55 TMR2IE TMR1IE 55 TMR2IP TMR1IP 55 CCP4IF CCP3IF 55 CCP4IE CCP3IE 55 CCP4IP CCP3IP 55 TRISG1 TRISG0 © 2009 Microchip Technology Inc. ...
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... PWM mode: PxA, PxC active-low; PxB, PxD active-low Note 1: Implemented only for ECCP1 and ECCP2; same as ‘1010’ for ECCP3. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY The control register for the Enhanced CCP module is shown in Register 18-1. It differs from the CCP4CON/ CCP5CON registers in that the two Most Significant bits are implemented to control PWM functionality ...
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... Timers depending on the mode selected. Timer1 and Timer3 are available for modules in Capture or Compare modes, while Timer2 and Timer4 are available for modules in PWM mode. Additional details on timer resources are provided in Section 17.1.1 “CCP Modules Resources”. © 2009 Microchip Technology Inc. and Timer ...
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... ECCP2 00xx 11xx Dual PWM 10xx 11xx Quad PWM x1xx 11xx Legend Don’t care. Shaded cells indicate pin assignments not used by ECCP2 in a given mode. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY RC2 RE6 RE5 All PIC18F6XJ10/6XJ15 Devices: RE6 RE5 ...
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... N/A N/A P3D N/A N/A RG3/CCP4 RH7/AN15 RH6/AN14 RG3/CCP4 P3B RH6/AN14 P3D P3B P3C RG3/CCP4 RH7/AN15 RH6/AN14 RG3/CCP4 RH5/AN13 RH4/AN12 RG3/CCP4 RH5/AN13 RH4/AN12 P3D RH5/AN13 RH4/AN12 CCP” mode as in Tables 18-1 for PWM Operation” or © 2009 Microchip Technology Inc. ...
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... PR2 Note: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY waveforms do not exactly match the standard PWM waveforms, but are instead offset by one full instruction cycle ( ...
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... The Half-Bridge and Full-Bridge Output modes are covered in detail in the sections that follow. The general relationship of the outputs in all configurations is summarized in Figure 18-2. ) bits 9.77 kHz 39.06 kHz FFh FFh 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 © 2009 Microchip Technology Inc. ...
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... Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: The dead-band delay is programmed using the ECCP1DEL register (Section 18.4.6 “Programmable Dead-Band Delay”). © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 0 Duty Cycle Period (1) (1) Delay Delay ...
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... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: The output signals are shown as active-high. V+ PIC18F87J10 FET Driver P1A FET Driver P1B V- V+ FET Driver Load FET Driver V- HALF-BRIDGE PWM OUTPUT Period Period td (1) ( Load + V - FET Driver FET Driver © 2009 Microchip Technology Inc. ...
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... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: The output signal is shown as active-high. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY P1A, P1B, P1C and P1D outputs are multiplexed with the port pins as described in Table 18-1, Table 18-2 and Table 18-3 ...
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... Reduce PWM for a PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. QC FET Driver FET Driver QD © 2009 Microchip Technology Inc. ...
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... Note 1: All signals are shown as active-high the turn-on delay of power switch, QC, and its driver the turn-off delay of power switch, QD, and its driver. OFF © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY (1) Period DC , depending on the Timer2 prescaler value. The modulated P1B and P1D signals OSC ...
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... R/W-0 R/W-0 PxDC4 PxDC3 PxDC2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared / cycles, between the scheduled and actual time for a PWM OSC OSC also trigger a shutdown. The R/W-0 R/W-0 PxDC1 PxDC0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Independent of the P1RSEN bit setting, if the auto-shutdown source is one of the comparators, the shutdown condition is a level. The ECCP1ASE bit cannot be cleared as long as the cause of the shutdown persists. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY R/W-0 R/W-0 R/W-0 ECCPxAS0 ...
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... PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Resumes ECCP1ASE Cleared by Firmware PWM Resumes © 2009 Microchip Technology Inc. ...
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... Select the auto-shutdown sources using the ECCPxAS<2:0> bits. • Select the shutdown states of the PWM output pins using the PSSxAC<1:0> and PSSxBD<1:0> bits. • Set the ECCPxASE bit (ECCPxAS<7>). © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 8. If auto-restart operation is required, set the PxRSEN bit (ECCPxDEL<7>). 9. ...
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... BOR 54 TMR2IF TMR1IF 55 TMR2IE TMR1IE 55 TMR2IP TMR1IP 55 — TMR3IF CCP2IF 55 — TMR3IE CCP2IE 55 — TMR3IP CCP2IP 55 CCP4IF CCP3IF 55 CCP4IE CCP3IE 55 CCP4IP CCP3IP 55 TRISB1 TRISB0 56 TRISC1 TRISC0 56 TRISE1 TRISE0 56 TRISG1 TRISG0 56 TRISH1 TRISH0 55, CCPxM0 55 55, 57 PxDC1 PxDC0 57 © 2009 Microchip Technology Inc. ...
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... SSP1CON1 SSP2CON1 control the same features for two different modules. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 19.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four ...
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... SSPxBUF and the SSPxIF interrupt is set. During transmission, double-buffered. A write to SSPxBUF will write to both SSPxBUF and SSPxSR. R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) the SSPxBUF is not R-0 R bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY R/W-0 R/W-0 R/W-0 CKP ...
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... Example 19-1 shows the loading of the SSPxBUF (SSPxSR) transmission. The SSPxSR is not directly readable or writable and can only be accessed by addressing the SSPxBUF register. Additionally, the SSPxSTAT register indicates the various status conditions. © 2009 Microchip Technology Inc. completed for data ...
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... Serial Input Buffer (SSPxBUF) Shift Register (SSPxSR) LSb MSb PROCESSOR 1 © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Any serial port function that is not desired may be overridden by programming the corresponding Data Direction (TRIS) register to the opposite value. 19.3.4 TYPICAL CONNECTION Figure 19-2 shows a typical connection between two microcontrollers ...
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... SMP bit. The time when the SSPxBUF is loaded with the received data is shown. bit 2 bit 5 bit 4 bit 1 bit 3 bit 2 bit 5 bit 4 bit 3 bit Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2009 Microchip Technology Inc. ...