PIC18F66J15-I/PT Microchip Technology, PIC18F66J15-I/PT Datasheet - Page 229
![IC PIC MCU FLASH 48KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F66J15-I/PT
Manufacturer Part Number
PIC18F66J15-I/PT
Description
IC PIC MCU FLASH 48KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F63J11-IPT.pdf
(36 pages)
3.PIC18F85J10-IPT.pdf
(410 pages)
4.PIC18F85J10-IPT.pdf
(10 pages)
5.PIC18F85J10-IPT.pdf
(10 pages)
6.PIC18F85J10-IPT.pdf
(8 pages)
7.PIC18F66J15-IPT.pdf
(400 pages)
Specifications of PIC18F66J15-I/PT
Program Memory Type
FLASH
Program Memory Size
96KB (48K x 16)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
SPI/I2C/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
50
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Package
64TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F66J15-I/PT
Manufacturer:
TI/CC
Quantity:
1 500
Company:
Part Number:
PIC18F66J15-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F66J15-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F63J11-IPT PDF datasheet #2
- PIC18F85J10-IPT PDF datasheet #3
- PIC18F85J10-IPT PDF datasheet #4
- PIC18F85J10-IPT PDF datasheet #5
- PIC18F85J10-IPT PDF datasheet #6
- PIC18F66J15-IPT PDF datasheet #7
- Current page: 229 of 410
- Download datasheet (7Mb)
19.4.8
To initiate a Start condition, the user sets the Start
Enable bit, SEN (SSPxCON2<0>). If the SDAx and
SCLx pins are sampled high, the Baud Rate Generator
is reloaded with the contents of SSPxADD<6:0> and
starts its count. If SCLx and SDAx are both sampled
high when the Baud Rate Generator times out (T
the SDAx pin is driven low. The action of the SDAx
being driven low while SCLx is high is the Start condi-
tion and causes the S bit (SSPxSTAT<3>) to be set.
Following this, the Baud Rate Generator is reloaded
with the contents of SSPxADD<6:0> and resumes its
count. When the Baud Rate Generator times out
(T
matically cleared by hardware; the Baud Rate Generator
is suspended, leaving the SDAx line held low and the
Start condition is complete.
FIGURE 19-21:
© 2009 Microchip Technology Inc.
BRG
), the SEN bit (SSPxCON2<0>) will be auto-
I
CONDITION TIMING
2
C MASTER MODE START
Write to SEN bit occurs here
FIRST START BIT TIMING
SDAx
SCLx
SDAx = 1,
SCLx = 1
T
BRG
BRG
),
Set S bit (SSPxSTAT<3>)
T
S
BRG
PIC18F87J10 FAMILY
At completion of Start bit,
hardware clears SEN bit
19.4.8.1
If the user writes the SSPxBUF when a Start sequence
is in progress, the WCOL bit is set and the contents of
the buffer are unchanged (the write doesn’t occur).
and sets SSPxIF bit
Note:
Note:
Write to SSPxBUF occurs here
T
BRG
1st bit
If at the beginning of the Start condition, the
SDAx and SCLx pins are already sampled
low, or if during the Start condition, the
SCLx line is sampled low before the SDAx
line is driven low, a bus collision occurs, the
Bus Collision Interrupt Flag, BCLxIF, is set,
the Start condition is aborted and the I
module is reset into its Idle state.
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPxCON2 is disabled until the Start
condition is complete.
WCOL Status Flag
T
BRG
2nd bit
DS39663F-page 227
2
C
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