PIC18F66J15-I/PT Microchip Technology, PIC18F66J15-I/PT Datasheet - Page 405

• Manufacturer Part Number: PIC18F66J15-I/PT
• Description: IC PIC MCU FLASH 48KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F66J15-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 96KB (48K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SSPOV Status Flag ......................................................... 229
SSPxSTAT Register
SSx .................................................................................. 193
Stack Full/Underflow Resets .............................................. 65
SUBFSR .......................................................................... 339
SUBFWB .......................................................................... 328
SUBLW ............................................................................ 329
SUBULNK ........................................................................ 339
SUBWF ............................................................................ 329
SUBWFB .......................................................................... 330
SWAPF ............................................................................ 330
T
Table Pointer Operations (table) ........................................ 88
Table Reads/Table Writes ................................................. 65
TBLRD ............................................................................. 331
TBLWT ............................................................................. 332
Timer0 .............................................................................. 151
Timer1 .............................................................................. 155
Timer2 .............................................................................. 161
Timer3 .............................................................................. 163
© 2009 Microchip Technology Inc.
R/W Bit ............................................................. 209, 211
Associated Registers ............................................... 153
Operation ................................................................. 152
Overflow Interrupt .................................................... 153
Prescaler .................................................................. 153
Prescaler Assignment (PSA Bit) .............................. 153
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 153
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 152
Source Edge Select (T0SE Bit) ................................ 152
Source Select (T0CS Bit) ......................................... 152
16-Bit Read/Write Mode ........................................... 157
Associated Registers ............................................... 159
Interrupt .................................................................... 158
Low-Power Option ................................................... 157
Operation ................................................................. 156
Oscillator .......................................................... 155, 157
Oscillator, as Secondary Clock .................................. 34
Overflow Interrupt .................................................... 155
Resetting, Using the ECCP
Special Event Trigger (ECCP) ................................. 180
TMR1H Register ...................................................... 155
TMR1L Register ....................................................... 155
Use as a Clock Source ............................................ 157
Use as a Real-Time Clock ....................................... 158
Associated Registers ............................................... 162
Interrupt .................................................................... 162
Operation ................................................................. 161
Output ...................................................................... 162
PR2 Register ............................................................ 181
TMR2 to PR2 Match Interrupt .................................. 181
16-Bit Read/Write Mode ........................................... 165
Associated Registers ............................................... 165
Operation ................................................................. 164
Oscillator .......................................................... 163, 165
Overflow Interrupt ............................................ 163, 165
Special Event Trigger (ECCP) ................................. 165
TMR3H Register ...................................................... 163
TMR3L Register ....................................................... 163
Switching Assignment ...................................... 153
Layout Considerations ..................................... 158
Special Event Trigger ...................................... 158
PIC18F87J10 FAMILY
Timer4 ............................................................................. 167
Timing Diagrams
Associated Registers ............................................... 168
MSSP Clock Shift .................................................... 168
Operation ................................................................. 167
Postscaler. See Postscaler, Timer4.
PR4 Register ........................................................... 167
Prescaler. See Prescaler, Timer4.
TMR4 Register ........................................................ 167
TMR4 to PR4 Match Interrupt .......................... 167, 168
A/D Conversion ....................................................... 382
Asynchronous Reception ......................................... 252
Asynchronous Transmission ................................... 250
Asynchronous Transmission (Back to Back) ........... 250
Automatic Baud Rate Calculation ............................ 248
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 253
Baud Rate Generator with Clock Arbitration ............ 226
BRG Overflow Sequence ........................................ 248
BRG Reset Due to SDAx Arbitration During
Bus Collision During a Repeated Start
Bus Collision During a Repeated Start
Bus Collision During a Start Condition
Bus Collision During a Stop
Bus Collision During a Stop
Bus Collision During Start Condition
Bus Collision for Transmit and Acknowledge .......... 233
Capture/Compare/PWM (Including
CLKO and I/O .......................................................... 366
Clock Synchronization ............................................. 219
Clock/Instruction Cycle .............................................. 66
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 373
Example SPI Master Mode (CKE = 1) ..................... 374
Example SPI Slave Mode (CKE = 0) ....................... 375
Example SPI Slave Mode (CKE = 1) ....................... 376
External Clock (All Modes Except PLL) ................... 364
External Memory Bus for Sleep
External Memory Bus for TBLRD
Fail-Safe Clock Monitor ........................................... 291
First Start Bit Timing ................................................ 227
Full-Bridge PWM Output .......................................... 185
Half-Bridge PWM Output ......................................... 184
I
I
I
I
I
2
2
2
2
2
C Acknowledge Sequence .................................... 232
C Bus Data ............................................................ 377
C Bus Start/Stop Bits ............................................ 377
C Master Mode (7 or 10-Bit Transmission) ........... 230
C Master Mode (7-Bit Reception) ......................... 231
Normal Operation ............................................ 253
Start Condition ................................................. 235
Condition (Case 1) ........................................... 236
Condition (Case 2) ........................................... 236
(SCLx = 0) ....................................................... 235
Condition (Case 1) ........................................... 237
Condition (Case 2) ........................................... 237
(SDAx Only) ..................................................... 234
ECCP Modules) ............................................... 372
(Master/Slave) ................................................. 381
(Master/Slave) ................................................. 381
(Extended Microcontroller Mode) ............ 102, 104
(Extended Microcontroller Mode) ............ 102, 104
DS39663F-page 403