PIC18F66J15-I/PT Microchip Technology, PIC18F66J15-I/PT Datasheet - Page 289

• Manufacturer Part Number: PIC18F66J15-I/PT
• Description: IC PIC MCU FLASH 48KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F66J15-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 96KB (48K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.2
For PIC18F87J10 family devices, the WDT is driven by
the INTRC oscillator. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period is
4 ms and has the same stability as the INTRC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is selected
by a multiplexor, controlled by the WDTPS bits in Config-
uration Register 2H. Available periods range from about
4 ms to 135 seconds (2.25 minutes depending on
voltage, temperature and WDT postscaler). The WDT
and postscaler are cleared whenever a SLEEP or
CLRWDT instruction is executed, or a clock failure
(primary or Timer1 oscillator) has occurred.
FIGURE 24-1:
REGISTER 24-9:
TABLE 24-3:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-1
bit 0
Note 1:
RCON
WDTCON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
Name
All Device Resets
INTRC Oscillator
U-0
—
WDTPS<3:0>
Watchdog Timer (WDT)
This bit has no effect if the Configuration bit, WDTEN, is enabled.
SWDTEN
CLRWDT
Sleep
Unimplemented: Read as ‘0’
SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is off
IPEN
Bit 7
SUMMARY OF WATCHDOG TIMER REGISTERS
—
U-0
—
WDT BLOCK DIAGRAM
WDTCON: WATCHDOG TIMER CONTROL REGISTER
Bit 6
Enable WDT
—
—
W = Writable bit
‘1’ = Bit is set
U-0
—
WDT Counter
Bit 5
—
—
÷128
INTRC Control
4
Bit 4
U-0
Programmable Postscaler
—
RI
—
1:1 to 1:32,768
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Bit 3
PIC18F87J10 FAMILY
TO
—
24.2.1
The WDTCON register (Register 24-9) is a readable
and writable register. The SWDTEN bit enables or dis-
ables WDT operation. This allows software to override
the WDTEN Configuration bit and enable the WDT only
if it has been disabled by the Configuration bit.
U-0
—
Note 1: The CLRWDT and SLEEP instructions
2: When a CLRWDT instruction is executed,
Bit 2
PD
WDT
—
CONTROL REGISTER
(1)
clear the WDT and postscaler counts
when executed.
the postscaler count will be cleared.
Reset
U-0
—
Bit 1
POR
—
x = Bit is unknown
SWDTEN
U-0
Bit 0
BOR
—
DS39663F-page 287
Wake-up from
Power-Managed
Modes
WDT
Reset
Reset Values
SWDTEN
on page
R/W-0
54
54
bit 0
(1)