PIC18F66J15-I/PT Microchip Technology, PIC18F66J15-I/PT Datasheet - Page 235

• Manufacturer Part Number: PIC18F66J15-I/PT
• Description: IC PIC MCU FLASH 48KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F66J15-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 96KB (48K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.4.14
While in Sleep mode, the I
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
19.4.15
A Reset disables the MSSP module and terminates the
current transfer.
19.4.16
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I
be taken when the P bit (SSPxSTAT<4>) is set, or the
bus is Idle, with both the S and P bits clear. When the
bus is busy, enabling the MSSP interrupt will generate
the interrupt when the Stop condition occurs.
In multi-master operation, the SDAx line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed in
hardware with the result placed in the BCLxIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
• A Repeated Start Condition
• An Acknowledge Condition
FIGURE 19-27:
© 2009 Microchip Technology Inc.
SDAx
SCLx
BCLxIF
SLEEP OPERATION
EFFECTS OF A RESET
MULTI-MASTER MODE
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
2
C module can receive
Data changes
while SCLx = 0
2
C bus may
SDAx released
by master
SDAx line pulled low
by another source
PIC18F87J10 FAMILY
19.4.17
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDAx pin, arbitration takes place when the master
outputs a ‘1’ on SDAx, by letting SDAx float high and
another master asserts a ‘0’. When the SCLx pin floats
high, data should be stable. If the expected data on
SDAx is a ‘1’ and the data sampled on the SDAx
pin = 0, then a bus collision has taken place. The
master will set the Bus Collision Interrupt Flag, BCLxIF,
and reset the I
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDAx and SCLx lines are deasserted and
the SSPxBUF can be written to. When the user services
the bus collision Interrupt Service Routine and if the I
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge condition
was in progress when the bus collision occurred, the con-
dition is aborted, the SDAx and SCLx lines are
deasserted and the respective control bits in the
SSPxCON2 register are cleared. When the user services
the bus collision Interrupt Service Routine and if the I
bus is free, the user can resume communication by
asserting a Start condition.
The master will continue to monitor the SDAx and SCLx
pins. If a Stop condition occurs, the SSPxIF bit will be set.
A write to the SSPxBUF will start the transmission of
data at the first data bit regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the deter-
mination of when the bus is free. Control of the I
can be taken when the P bit is set in the SSPxSTAT
register, or the bus is Idle and the S and P bits are
cleared.
MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
2
C port to its Idle state (Figure 19-27).
Sample SDAx. While SCLx is high,
data doesn’t match what is driven
by the master.
Bus collision has occurred.
Set bus collision
interrupt (BCLxIF)
DS39663F-page 233
2
C bus
2
2
C
C