PIC18F66J15-I/PT Microchip Technology, PIC18F66J15-I/PT Datasheet - Page 369

• Manufacturer Part Number: PIC18F66J15-I/PT
• Description: IC PIC MCU FLASH 48KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F66J15-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 96KB (48K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 27-6:
TABLE 27-7:
© 2009 Microchip Technology Inc.
150
151
153
154
155
161
162
162A
163
166
167
168
170
170A
Param
No
AD<7:0>
A<19:8>
OSC1
BA0
ALE
OE
CE
TadV2aIL
TaIL2adl
B
B
TaIL2oeL
ToeH2adD OE ↑ to A/D Driven
TadV2oeH Least Significant Data Valid Before OE ↑
TadV2oeH Most Significant Data Valid Before OE ↑
ToeH2adI
TaIH2aIH
T
Toe
TubH2oeH BA0 = 0 Valid Before OE ↑
TubL2oeH BA0 = 1 Valid Before OE ↑
ACC
Symbol
A
A
01
02
PROGRAM MEMORY FETCH TIMING REQUIREMENTS (8-BIT)
Address Out Valid to ALE ↓ (address setup time)
ALE ↓ to Address Out Invalid (address hold time)
BA0 ↑ to Most Significant Data Valid
BA0 ↓ to Least Significant Data Valid
ALE ↓ to OE ↓
(data setup time
(data setup time)
OE ↑ to Data in Invalid (data Hold Time)
ALE ↑ to ALE ↑ (cycle time)
Address Valid to Data Valid
OE ↓ to Data Valid
Q1
PROGRAM MEMORY FETCH TIMING DIAGRAM (8-BIT)
Address
Address
150
151
Characteristics
Q2
155
167
168
153
Q3
166
170A
Data
PIC18F87J10 FAMILY
162A
154
Q4
170
0.25 T
0.25 T
0.125 T
0.5 T
163
0.125 T
0.125 T
0.125 T
0.25 T
0.5 T
Data
162
Min
CY
20
—
—
CY
CY
5
0
CY
CY
– 10
CY
– 10
CY
CY
CY
+ 20
– 5
161
Q1
Typ
T
—
—
—
—
—
—
—
—
—
—
—
—
—
CY
0.125 T
DS39663F-page 367
Address
Address
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
CY
Q2
+ 5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns