PIC18F66J15-I/PT Microchip Technology, PIC18F66J15-I/PT Datasheet - Page 141

• Manufacturer Part Number: PIC18F66J15-I/PT
• Description: IC PIC MCU FLASH 48KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F66J15-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 96KB (48K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 11-11:
TABLE 11-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
© 2009 Microchip Technology Inc.
PORTE
LATE
TRISE
PORTG
Legend: Shaded cells are not used by PORTE.
Note 1:
RE6/AD14/
P1B
RE7/AD15/
ECCP2/P2A
Legend:
Note 1:
Pin Name
Name
2:
3:
4:
Unimplemented on 64-pin devices, read as ‘0’.
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin devices only).
External memory interface I/O takes priority over all other digital and PSP I/O.
Available on 80-pin devices only.
Alternate assignment for ECCP2/P2A when the CCP2MX Configuration bit is cleared (all devices in Microcontroller mode).
TRISE7
LATE7
RDPU
Bit 7
RE7
ECCP2
Function
AD14
AD15
P1B
P2A
PORTE FUNCTIONS (CONTINUED)
RE6
RE7
(1)
(4)
(3)
(3)
(4)
TRISE6
LATE6
REPU
Bit 6
RE6
Setting
TRIS
0
1
x
x
0
0
1
x
x
0
1
0
RJPU
TRISE5
LATE5
Bit 5
I/O
RE5
O
O
O
O
O
O
O
I
I
I
I
I
(1)
Type
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
I/O
ST
ST
ST
TRISE4
LATE4
Bit 4
RE4
RG4
LATE<6> data output.
PORTE<6> data input.
External memory interface, address/data bit 14 output.
External memory interface, data bit 14 input.
ECCP1 Enhanced PWM output, Channel B; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATE<7> data output.
PORTE<7> data input.
External memory interface, address/data bit 15 output.
External memory interface, data bit 15 input.
CCP2 compare output and CCP2 PWM output; takes priority over
port data.
CCP2 capture input.
ECCP2 Enhanced PWM output, Channel A; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
PIC18F87J10 FAMILY
TRISE3
LATE3
Bit 3
RG3
RE3
TRISE2
LATE2
Bit 2
RG2
RE2
Description
TRISE1
LATE1
Bit 1
RE1
RG1
(2)
(2)
TRISE0
LATE0
Bit 0
RG0
DS39663F-page 139
RE0
(2)
(2)
on page
Values
Reset
56
56
56
56