PIC18F66J15-I/PT Microchip Technology, PIC18F66J15-I/PT Datasheet - Page 271

• Manufacturer Part Number: PIC18F66J15-I/PT
• Description: IC PIC MCU FLASH 48KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F66J15-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 96KB (48K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

© 2009 Microchip Technology Inc.
21.7
The A/D Converter in the PIC18F87J10 family of
devices includes a self-calibration feature which com-
pensates for any offset generated within the module.
The calibration process is automated and is initiated by
setting the ADCAL bit (ADCON0<7>). The next time
the GO/DONE bit is set, the module will perform a
“dummy” conversion (that is, with reading none of the
input channels) and store the resulting value internally
to compensate for offset. Thus, subsequent offsets will
be compensated.
The calibration process assumes that the device is in a
relatively steady-state operating condition. If A/D
calibration is used, it should be performed after each
device Reset or if there are other major changes in
operating conditions.
21.8
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed
mode.
TABLE 21-2:
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCP2CON
PORTA
TRISA
PORTF
TRISF
PORTH
TRISH
Legend:
Note 1:
Name
(1)
(1)
A/D Converter Calibration
Operation in Power-Managed
Modes
This register is not implemented on 64-pin devices.
— = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
GIE/GIEH PEIE/GIEL TMR0IE
A/D Result Register High Byte
A/D Result Register Low Byte
OSCFIF
OSCFIE
OSCFIP
TRISF5
TRISH7
ADCAL
PSPIE
PSPIP
PSPIF
ADFM
P2M1
Bit 7
RH7
SUMMARY OF A/D REGISTERS
RF7
—
—
—
TRISH6
TRISF4
P2M0
CMIF
CMIE
CMIP
ADIF
ADIE
ADIP
Bit 6
RH6
RF6
—
—
—
—
—
TRISH5
TRISA5
TRISF5
VCFG1
ACQT2
DC2B1
RC1IF
RC1IE
RC1IP
CHS3
Bit 5
RA5
RH5
RF5
—
—
—
TRISH4
TRISA4
TRISF4
VCFG0
ACQT1
DC2B0
INT0IE
TX1IF
TX1IE
TX1IP
CHS3
Bit 4
RA4
RH4
RF4
—
—
—
PIC18F87J10 FAMILY
CCP2M3
SSP1IE
SSP1IP
TRISA3
TRISH3
SSP1IF
BCL1IF
BCL1IE
BCL1IP
TRISF3
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT<2:0> and
ADCS<2:0> bits in ADCON2 should be updated in
accordance with the power-managed mode clock that
will be used. After the power-managed mode is entered
(either of the power-managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
mode clock source until the conversion has been com-
pleted. If desired, the device may be placed into the
corresponding power-managed Idle mode during the
conversion.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in the Sleep mode requires the A/D RC clock
to be selected. If bits, ACQT<2:0>, are set to ‘000’ and
a conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode. The IDLEN and
SCS bits in the OSCCON register must have already
been cleared prior to starting the conversion.
PCFG3
ACQT0
CHS1
RBIE
Bit 3
RA3
RF3
RH3
CCP2M2
TMR0IF
CCP1IF
CCP1IE
CCP1IP
TRISA2
TRISH2
PCFG2
TRISF2
ADCS2
CHS0
Bit 2
RH2
RA2
RF2
—
—
—
GO/DONE
CCP2M1
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
TRISA1
TRISF1
TRISH1
PCFG1
ADCS1
INT0IF
Bit 1
RH1
RA1
RF1
DS39663F-page 269
CCP2M0
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
TRISH0
TRISA0
PCFG0
ADCS0
ADON
RBIF
Bit 0
RA0
RH0
—
—
on page
Values
Reset
53
55
55
55
55
55
55
54
54
54
54
54
55
56
56
56
56
56
56