MT48H8M32LFB5-10 TR Micron Technology Inc, MT48H8M32LFB5-10 TR Datasheet - Page 5

• Manufacturer Part Number: MT48H8M32LFB5-10 TR
• Description: IC SDRAM 256MBIT 100MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M32LFB5-10 TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 3: Cross Reference For VFBGA Device Marking
FBGA Part Number System
General Description
PDF: 09005aef80d460f2/Source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. G 6/05
Part Number
MT48LC8M32LFF5-75
MT48LC8M32LFF5-8
MT48LC8M32LFF5-10
MT48LC8M32LFB5-75
MT48LC8M32LFB5-8
MT48LC8M32LFB5-10
MT48V8M32LFF5-75
MT48V8M32LFF5-8
MT48V8M32LFF5-10
MT48V8M32LFB5-75
MT48V8M32LFB5-8
MT48V8M32LFB5-10
MT48H8M32LFF5-75
MT48H8M32LFF5-8
MT48H8M32LFF5-10
MT48H8M32LFB5-75
MT48H8M32LFB5-8
MT48H8M32LFB5-10
Due to space limitations, FBGA-packaged components have an abbreviated part mark-
ing that is different from the part number. For a quick conversion of an FBGA code, see
the FBGA part marking decoder on Micron’s Web site, www.micron.com/decoder.
The Micron
containing 268,435,456 bits. It is internally configured as a quad-bank DRAM with a syn-
chronous interface (all signals are registered on the positive edge of the clock signal,
CLK). Each of the 67,108,864-bit banks is organized as 4,096 rows by 512 columns by 32
bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0–A11 select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths of 1, 2, 4, or 8 loca-
tions, or the full page, with a burst terminate option. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
sequence.
The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed oper-
ation. This architecture is compatible with the 2n rule of prefetch architectures, but it
also allows the column address to be changed on every clock cycle to achieve a high-
V
3.3V/3.3V
3.3V/3.3V
3.3V/3.3V
3.3V/3.3V
3.3V/3.3V
3.3V/3.3V
2.5V/2.5V
2.5V/2.5V
2.5V/2.5V
2.5V/2.5V
2.5V/2.5V
2.5V/2.5V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
DD
/V
DD
®
Q
256Mb SDRAM is a high-speed CMOS, dynamic random-access memory
Architecture
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
VFBGA
256Mb: x32 Mobile SDRAM
FBGA Part Number System
©2003 Micron Technology, Inc. All rights reserved.
Production
Marking
D9FMQ
D9CCW
D9CCM
D9FMX
D9FMV
D9CCH
D9CCK
D9FMS
D9FMZ
D9CDC
D9CCZ
D9CCP
D9CDF
D9CCR
D9CCT
D9FNB
D9CDL
D9CDJ