MT48H8M32LFB5-10 TR Micron Technology Inc, MT48H8M32LFB5-10 TR Datasheet - Page 12

• Manufacturer Part Number: MT48H8M32LFB5-10 TR
• Description: IC SDRAM 256MBIT 100MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M32LFB5-10 TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5: Burst Definition Table
CAS Latency
PDF: 09005aef80d460f2/Source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. G 6/05
Notes: 1. For full-page accesses: y = 512.
The CAS latency is the delay, in clock cycles, between the registration of a READ com-
mand and the availability of the first piece of output data. The latency can be set to one,
two, or three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQs will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming that the clock cycle
time is such that all relevant access times are met, if a read command is registered at T0
Burst Length
2. For BL = 2, A1
3. For BL = 4, A2
4. For BL = 8, A3
5. For a full-page burst, the full row is selected and A0
6. Whenever a boundary of the block is reached within a given sequence above, the follow-
7. For BL = 1, A0
Full Page (y)
block.
the block.
the block.
ing access wraps within the block.
ignored.
2
4
8
Starting Column Address
–
–
–
–
A8 select the block-of-two burst; A0 selects the starting column within the
A8 select the block-of-four burst; A0-A1 select the starting column within
A8 select the block-of-eight burst; A0-A2 select the starting column within
A8 select the unique column to be accessed, and mode register bit M3 is
A2
0
0
0
0
1
1
1
1
n = A0-A11/9/8
(location
0-y)
A1
A1
0
0
1
1
0
0
1
1
0
0
1
1
12
A0
A0
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Type = Sequential
Cn + 3, Cn + 4...
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Order of Accesses Within a Burst
Cn, Cn + 1,
…Cn - 1,
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
Cn + 2
Cn…
–
256Mb: x32 Mobile SDRAM
0-1
1-0
A8 select the starting column.
©2003 Micron Technology, Inc. All rights reserved.
Register Definition
Type = Interleaved
Not Supported
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0