RF6001_1 RFMD [RF Micro Devices], RF6001_1 Datasheet - Page 65

• Manufacturer Part Number: RF6001_1
• Description: FRACTIONAL-N RF SYNTHESIZER WITH MODULATOR AND DIGITAL IF FILTER
• Manufacturer: RFMD [RF Micro Devices]

RX Blanking (BLANK) - Address 110011
DELAY - Address 110100
TX Data Control (DFILL) - Address 110101
Rev A3 DS050929
BLANK (16:14)
DELAY (15:14)
BLANK (11:6)
DFILL (14:10)
DELAY (13:8)
BLANK (5:0)
BLANK (13)
BLANK (12)
BLANK (17)
DELAY (7:0)
DELAY (17)
DELAY (16)
DFILL (9:5)
DFILL (4:0)
DFILL (17)
DFILL (16)
DFILL (15)
Location
Location
Location
AGC_DLY(5:0)
BLK_DLY(5:0)
DCAD_2(5:0)
RD_DLY(4:0)
RU_DLY(4:0)
G_CNT(2:0)
G_DLY(4:0)
Bit Name
Bit Name
ADCCLK_2
Bit Name
AD2EN_2
reserved
reserved
reserved
ADEN_2
DE_INIT
G_DEF
FCLR
MSR
(1:0)
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support, contact RFMD at ([phone] or [e-mail].
Default
Default
Default
000
18h
26h
25h
11
0
0
0
0
0
1
1
0
0
0
0
0
Controls the behavior of the MS pulse in a GPRS serial TX burst, if the RF6001 is the bus
0=MS resume disabled
1=MS resume enabled
This field allows variable blanking of user data bits.
In FIFO, this bit is only active in MS PULSE mode (TXF=2). On the rising edge of MS, the
Power on default of the differential encoder starting value.
reserved, program to zero (0).
Channel filter blanking delay. Delay=BLK_DLY*3.69us.
RX output blanking delay. Delay=AGC_DLY*3.69us.
Second DC Correction System Enable
Second DC Correction System Enable 2
DC Correction System Clock Rate, after adapt time is elapsed. Default is 13MHz/48, for
Fine DC correction fast adapt time. Programs in steps of (48/13)us. Default is 70us.
reserved, program to zero (0).
If FCLR is set high, the FIFO will be cleared. Once the operation is complete, the SDI bit
G_DEF is the input value to the GMSK modulator when the modulator data input is not
reserved, program to zero (0).
This field will increase the latency of the GMSK modulator in 1/16 symbol increments.
In UAM mode, RD_DLY can be used to delay the ramp down in 1/8S increments, relative
In UAM mode, RU_DLY can be used to delay the ramp up in 1/8S increments, relative to
master. If MSR is high, then an MS pulse will occur every 16MCK clock pulse, even
between GPRS bursts. If MSR is low, the MS pulse will appear with the first MCK
pulse of each burst, regardless of how MCK pulses have elapsed since the last MS
pulse.
FIFO will ignore the first GCNT bits on the serial interface. In TX serial mode, the
GMSK differential encoder and modulator will ignore the first GCNT bits. During this
time, G_DEF will be gated to the modulator. In GPRS mode, GCNT is only active in
the first burst.
0=DC correction system will continue to operate after the adapt time is elapsed, at
the rate defined by ADCLK.
1=DC correction will stop at the end of the adapt time.
slowest adapt.
00=13MHz
01=13MHz/2
10=13MHz/24
11=13MHz/48
will automatically revert low.
active.
The modulator delay can be adjusted from 12.2 quarter symbol times (qst) to
19.95qst. G_DLY cannot be used without EALGN.
to the falling edge of TXST. This field is not used if UAM is low.
the rising edge of TXST. Note that this field is only used in GPRS mode because PAT
always controls the first ramp up delay.
Part of the POLARIS™ TOTAL RADIO™ Solution
Function
Function
Function
RF6001
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