RF6001_1 RFMD [RF Micro Devices], RF6001_1 Datasheet - Page 44

• Manufacturer Part Number: RF6001_1
• Description: FRACTIONAL-N RF SYNTHESIZER WITH MODULATOR AND DIGITAL IF FILTER
• Manufacturer: RFMD [RF Micro Devices]

RF6001
Part of the POLARIS™ TOTAL RADIO™ Solution
In GMSK mode, there is a latency of approximately 12qst (12.2qst, actually) from the center of a data symbol entering the
modulator to the maximum RF effect of the symbol. Thus DAC1 is aligned with the “Data at output” field and is 12qst delayed
from the data at the input of the GMSK modulator. The data at the input of the modulator is delayed by 6qst from the data at
the FIFO output by G_DLY. Thus the total delay is 18qst and matches the 8PSK delay.
Note that none of the tail bits are punctured.
GMSK to GMSK, EALGN=1, “Normal” Serial Mode
If the serial mode interface is used instead of the FIFO then the diagram below presents the transition. MD_DLY2 is active in
serial mode as well as FIFO mode. The rules for MD_DLY2 are as follows:
Data changes at MDI on the rising edges of MCK and is read on the falling edges of MCK. In this example G_DLY is set to 6qst
so the Modulator input is delayed a net of 8 qst from the data at MDI.
In this diagram G_CNT is set to three to blank the first three serial bits from the baseband system. MD_DLY2 is set to 1 to
exactly meet the ETSI 8.25 symbol guard time. G_DEF fills the three garbage symbols and the 1 qst from MD_DLY2.
There will be a phase glitch at the start of G_DLY due to the quarter bit shift. This will occur during the ramp down. As in the last
case this should not be a problem if the previous four symbols are all 1s or 0s.
Note that the falling edge of TX_ST is delayed 1qst. This is not a timing mask issue as there is no timing mask between GPRS
bursts other than the maximum power level.
If the serial mode interface is used with MS then the only difference is that MS will pulse on the last G_CNT count.
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Data Alignment
Modulator
DAC1
TXST
at RF
Input
MCK
MDI
tail
0
guard
tail
1
0
G_DLY
guard
data
tail
0
1
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guard
guard
tail
1
1
Center of
last tail bit
12 qst
guard
guard
MD_DLY2=1
tail
1
1
guard
guard
Clocks
Reset
tail
1
1
guard
G_DEF
garbage
1
X
guard
G_DLY
G_DEF
garbage
0
X
Garbage Bits
Ignored
G_CNT=3
garbage
guard
X
guard
G_DEF
tail
37qst
0
0
G_DEF
tail
0
tail
tail
0
0
G_DEF
data
tail
0
data
8qst
tail
0
data
tail
0
data
Desired center
of first tail bit
tail
0
tail
0
data
Rev A3 DS050929