RF6001_1 RFMD [RF Micro Devices], RF6001_1 Datasheet - Page 40

• Manufacturer Part Number: RF6001_1
• Description: FRACTIONAL-N RF SYNTHESIZER WITH MODULATOR AND DIGITAL IF FILTER
• Manufacturer: RFMD [RF Micro Devices]

RF6001
Part of the POLARIS™ TOTAL RADIO™ Solution
GMSK Ramp-Up
The diagram below presents the ramp up for GMSK in the FIFO mode of operation. The latency is the sum of G_DLY and the
basic GMSK latency of 12qst. The sum of the two is 18qst and is selected to match the 8PSK latency in this example. Any
glitch will occur when the clock resets at the end of G_DLY and thus is at a low power level. This allows G_DEF to be used for
the guard bits if desired. (Note that 8qst ramps have been used for these examples; 13qst or 16qst ramps could be used
equally well.)
If data is loaded with the serial mode system using MS, then the diagram below presents the operation of the system.
TX_EN is set to occur 18qst before the top of the ramp so as to not violate the ETSI time mask at the -30dBc point. MD_DLY1
is set to start the modulator 66qst plus G_DLY before TX_EN so that the first valid data symbol is the first tail symbol. G_CNT
will have to be set to one in this case so that the initial state of the differential encoder is set at the correct time. If the base-
band differential encoding is used then G_CNT does not matter.
Note that the user could also send the guard symbols if MD_DLY1 is further advanced.
Since the new data flow starts well in advance of the burst, then there should be no issue with phase transitions if the delay
from the rise of TX_ST to the end of MD_DLY1 is not an integer number of symbol times. Any such transition will occur at mini-
mum output power levels if MD_DLY1 is advanced far enough.
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Modulator
DAC1
TXEN
TXST
at RF
MCK
Data
Start
MS
Modulator
Serial GMSK Mode using MS, MCK and MS are Output from RF6001, EALGN=1
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at ([phone] or [e-mail].
DAC1
TXEN
TXST
at RF
Data
Start
MD_DLY
MCK starts
First MS pulse is
always blanked
TXENU
MD_DLY1
16 MCKs
TXENU
64qst
FIFO GMSK Start-up Mode, EALGN=1
G_DLY
clocks reset
First data
from FIFO
Modulator clock resets
PAT
PAT
G_DEF
G_DLY
6qst
G_DEF
G_DLY
PA Turns ON
First valid data
from baseband
16qst
12qst
PA Turns ON
2qst
18qst
max
12qst
2qst
tail
Latency of GMSK
mod complete
tail
Top of Ramp
tail
Latency of GMSK
mod complete
tail
tail
Top of Ramp
tail
Rev A3 DS050929