RF6001_1 RFMD [RF Micro Devices], RF6001_1 Datasheet - Page 28

• Manufacturer Part Number: RF6001_1
• Description: FRACTIONAL-N RF SYNTHESIZER WITH MODULATOR AND DIGITAL IF FILTER
• Manufacturer: RFMD [RF Micro Devices]

RF6001
Part of the POLARIS™ TOTAL RADIO™ Solution
PA Ramp Control
The RF6001 contains a PA ramp control system that operates through the DAC1 pin. The PA ramp control system is turned on
by programming PAEN bit to one (1). The user programs the minimum DAC1 level into the DAC1V register, the desired PA ramp
waveform sample values into the PAR registers, and a gain word into the PAG register.
A conceptual block diagram of the PA Ramp control system is illustrated below.
The timing diagram below illustrates a GSM transmit burst. In this case the GPRS_TX1 bit is programmed to zero (0). The trans-
mit VCO and PLL should be turned on and given sufficient time to lock prior to starting modulation and the PA ramp. The mod-
ulation and ramp sequence is initiated by taking the TXST pin high. This starts the TX modulator (after a delay set by
MD_DLY1), using data or modulation present on the GMSK modulation interface or stored in the First In First Out (FIFO), and
turns on DAC1/VRAMP DAC, set to the value in the DAC1V register (the minimum value). (If modulation is not desired, the mod-
ulation interface should be set to digital mode, and the TX input pins should be held inactive.) The TXEN pin is an output used
to enable the PA. This pin will go high after the rising edge of the TXST input pin with a delay programmed by the SDI field
TXENU.
The PA ramp waveform starts after time PAT relative to the rising edge of TXST. The 16 steps in the PAR registers (PARAMP3-
at the maximum value of the PA ramp waveform until TXST is taken low, at which point the PAR waveform is used to ramp the
DAC1 signal back down to the DAC1V value. The DAC and modulation shut off and the TXEN pin goes low after the ramp down
is completed and following a delay programmed by the SDI field TXEND. The DAC1 signal is defined by the following equation:
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PARAMP11) are swept at a rate of (12/13)μs with an interpolation by 2 to result in a rate of (6/13)μs per step. DAC1 remains
PA
system clock
RAMP
13MHz
=
TXEND
PAG PAR
--------------------------- -
(5:0)
(7:0)
PAT
PAR[15:0, 9:]
1024
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support, contact RFMD at ([phone] or [e-mail].
Ramp LUT
TXENU
⋅
Timer
(7:0)
TXST
pin
PAEN
+
DAC1V
------------------- -
65536
10
PAG(9:0)
10
10
DAC1V(9:0)
⋅
2.5V
10
10
10
PAEN
1
0
10
DAC1EN
DAC
PAEN
TXST
pin
DAC1
TXEN
pin
pin
Rev A3 DS050929