RF6001_1 RFMD [RF Micro Devices], RF6001_1 Datasheet - Page 34

• Manufacturer Part Number: RF6001_1
• Description: FRACTIONAL-N RF SYNTHESIZER WITH MODULATOR AND DIGITAL IF FILTER
• Manufacturer: RFMD [RF Micro Devices]

RF6001
Part of the POLARIS™ TOTAL RADIO™ Solution
Case 3: GMSK FIFO Clocking Signals Generated by Baseband, TXD_MODE=1, TXF=01
The FIFO will automatically clear under three conditions: 1) if the SDI reset field is programmed; 2) at the end of any transmis-
sion burst following the end of the ramp down; and, 3) if the SDI field FCLR is set. This will clear the contents of the FIFO mem-
ory and designate the next bit written as the first output bit of the FIFO. The baseband will then generate a clock of less than or
equal to 26MHz applied to MCK. On every rising edge of MCK, the baseband will assert an NRZ data bit on MDI if TXCKINV is
low. The RF6001 will read this data on every falling edge of MCK if TXCKINV is set low. If TXCKINV is set high, the baseband will
assert an NRZ data bit on the falling edge of MCK and the RF6001 will read this data if MS is high on every rising edge of MCK.
This data will be stored in a First In First Out (FIFO) register of length 1024 bits in the RF6001. The diagram below summarizes
this part of the interface.
Transmission is initiated by setting the TXST or TXEN pins to a logical high. If TX_ST is set high, an internal timer (TXENU) is pro-
grammed to delay the rise of TX_EN. A second timer (MD_DLY) determines then the modulation stored in the FIFO will begin to
be output relative to the rising edge of TX_ST. Data will be output at a 13MHz/48 rate. New data CAN be loaded into the FIFO
input while the output is active. The second diagram below summarizes the operation of the second step of this interface.
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Auto Clear
Auto Clear
MCKO
MCKO
Count
Count
FIFO
FIFO
MDI
MDI
T
CS
T
TXCKINV=1, TXF=01
TXCKINV=0, TXF=01
T
CWH
SU
1
1
2
2
T
CWL
T
H
3
3
4
4
Rev A3 DS050929