RF6001_1 RFMD [RF Micro Devices], RF6001_1 Datasheet - Page 64

• Manufacturer Part Number: RF6001_1
• Description: FRACTIONAL-N RF SYNTHESIZER WITH MODULATOR AND DIGITAL IF FILTER
• Manufacturer: RFMD [RF Micro Devices]

RF6001
Part of the POLARIS™ TOTAL RADIO™ Solution
SSI - Address 110001
64 of 70
SSI(17:16)
Location
SSI(8:7)
SSI(4:1)
SSI(15)
SSI(14)
SSI(13)
SSI(12)
SSI(11)
SSI(10)
SSI(9)
SSI(6)
SSI(5)
SSI(0)
MS_LEN(3:0)
CLKRM(1:0)
TXD_MODE
Bit Name
CLKRINV
TXF(1:0)
TXCKINV
MS_LOC
FS_LOC
EN_SEL
INTNEN
RXCKB
RXFSB
RX_T
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support, contact RFMD at ([phone] or [e-mail].
Default
00
00
0
0
0
0
0
0
0
0
0
0
0
CLKR Mode
0=CLKR is enabled when ENR=1, but operates only during the active data portion of
01=CLKR is enabled when ENR=1 and remains on regardless of the state of DBL.
1x=CLKR is always disabled.
Receive Clock Source
0=CLKR is an output
1=CLKR is an input
Receive Frame Sync Source
0=FSR is an output
1=FSR is an input
Frame Sync Location
0=FSR coincident with MSB of I data
1=FSR occurs on clock before MSB of I data
Receive SSI Mode
0=RXSSI starts with ENR
1=RXSSI starts with RXEN
RXSSI Trailing Clock Pulses. Adds clocks to the end of an RXSSI transfer.
0=No extra clock cycles are added to the end of an RXSSR transfer.
1=5 extra clock cycles are added to the end of an RXSSR transfer.
Inverts the CLKR signal.
0=Uninverted, normal polarity
1=Inverted polarity
0=Digital TX interface, MCK and MS are outputs
1=Digital TX interface, MCK and MS are inputs
Controls the FIFO Interface Modes
00=TX FIFO disabled
01=No MS mode. FIFO will shift in bits on every falling edge of MCK, regardless of the
10=MS FRAME mode. FIFO will shift in bits on every falling edge of MCK, if MS is high.
11=MS PULSE mode. At every MS pulse, the FIFO will shift in a predetermined number
TX Clock Invert
0=Data is latched on the falling edge of MCK
1=Data is latched on the rising edge of MCK
Test bit. Program to 0.
MS Pulse Length. In TXF=11 mode, MS_LEN controls the number of bits the TX FIFO will
MS_LEN=0: 4 bits
MS_LEN=1: 5 bits
MS_LEN=2: 6 bits
MS_LEN=3: 7 bits
MS_LEN=4: 8 bits
MS_LEN=5: 9 bits
MS Pulse Location
0=transfer of first data bit occurs on same clock period as the pulse on MS
1=transfer of first data bit occurs on the next clock period after the pulse on MS
TX Digital Interface Mode
the transfer (disabled during any blank data portion).
MS signal.
of bits. The position of MS, relative to the first data bit is controlled by MS_LOC. The
number of bits shifted in is determined by MS_LEN[4:0].
shift in, on every MS pulse.
MS_LEN=6: 10 bits
MS_LEN=7: 11 bits
MS_LEN=8: 12 bits
MS_LEN=9: 13 bits
MS_LEN=10: 14 bits
MS_LEN=11: 16 bits
Function
MS_LEN=12: 24 bits
MS_LEN=13: 26 bits
MS_LEN=14: 32 bits
MS_LEN=15: 48 bits
Rev A3 DS050929