RF6001_1 RFMD [RF Micro Devices], RF6001_1 Datasheet - Page 19

• Manufacturer Part Number: RF6001_1
• Description: FRACTIONAL-N RF SYNTHESIZER WITH MODULATOR AND DIGITAL IF FILTER
• Manufacturer: RFMD [RF Micro Devices]

Selection of RX Clocks and Sync as Inputs or Outputs
FSR can be configured as an input (RXFSB=1) or as an output (RXFSB=0).
CLKR can be configured as an input (RXCKB=1) or as an output (RXCKB=0).
If CLKR is an input, then:
1. There must be at least two CLKR periods before valid data is output.
2. FSR can be an input or an output.
3. If FSR is also an input, then there must be at least two CLKR periods before FSR is externally set.
If CLKR is an output then FSR must be an output as well.
Selection of RX Sync Location Relative to Data
The position of FSR relative to the I channel MSB can be set with the SDI bit FS_LOC. If FS_LOC is set false then the FSR pulse
occurs with the MSB of the I channel data as shown in all of the diagrams in the Digital RX SSI Mode section below. If FS_LOC
is set true then the FSR pulse will occur on the clock immediately before the MSB of the I channel data.
Selection of RX SSI Enable Method
The digital RX SSI can be enabled by two methods. The first method is a physical pin labeled ENR. If ENR is set high then the
RX SSI will activate two CLKR pulses after ENR rises. The sampling point of the digital filters is set by the position of RX_EN rel-
ative to the midamble and will not change with the position of ENR. The sample time of the SSI output word WILL move with the
edge of ENR.
If ENR is set low then the RX SSI will deactivate after the current data transfer completes. This mode is active if the SDI bit
EN_SEL is programmed low.
If EN_SEL is programmed high then the RX SSI activates with RX_EN high and deactivates with RX_EN low. All timing edges are
relative to RX_EN.
Summary of Digital RX SSI Modes
The various digital receive modes are explained in detail below.
RXMODE=000, DBL=0
In this mode the SSI provides one sample of I and one sample of Q for each GSM symbol period. The output data pattern on
DRI is 12 bits of I data followed by 12 bits of Q data followed by 24 blank bits. In this case FSR is (13/48)MHz=270.8333kbps
and CLKR is 13MHz.
The various CLKR modes are defined as follows: with CLKRM=00 and RXCKB=0, CLKR will shut down after the Q data transfer
completes until the next I data transfer to save power; with CLKRM=01 and RXCKB=0, CLKR is always enabled if ENR is true;
with CLKRM=1x, CLKR is always disabled.
The following diagram summarizes this mode of operation.
Rev A3 DS050929
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at ([phone] or [e-mail].
CLKR
FSR
DRI
FS_LOC=1
I(15)
I(14)
CLKR
FSR
DRI
Part of the POLARIS™ TOTAL RADIO™ Solution
FS_LOC=0
I(15)
I(14)
RF6001
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