RF6001_1 RFMD [RF Micro Devices], RF6001_1 Datasheet - Page 32

• Manufacturer Part Number: RF6001_1
• Description: FRACTIONAL-N RF SYNTHESIZER WITH MODULATOR AND DIGITAL IF FILTER
• Manufacturer: RFMD [RF Micro Devices]

RF6001
Part of the POLARIS™ TOTAL RADIO™ Solution
Digital Mode
Programming the TXAD bit high puts the GMSK modulation interface in digital mode, and the TXI input is disabled. The MS and
MCK signals can be generated by either the RF6001 or the baseband, as configured by SDI bit TXD_MODE.
The data on MDI can be differentially encoded by setting SDI bit TX_DE true. If the data has already been differentially encoded
by the baseband, the TX_DE should be set false to bypass the differential encoder.
TX_INV inverts the data at the output of the differential encoder.
The RF6001 also contains a 312 bit FIFO. The FIFO allows up to two timeslots of GMSK data to be loaded before the transmis-
sion begins.
Addition of Delay on MCK
The FIFO needs a rising edge on MCK to set the pointer before data is read on the falling edge of MCK. If MCK is inactive high
then there is no rising edge on the first transfer as MCK is already high.
A rising edge is thus created by ANDing MCK and MS. This is fine except at the end of the data transfer. At this point the base-
band simultaneously drops MS to zero and returns MCK to the inactive high state. If MCK occurs slightly earlier than MS then
there will be a glitch pulse from the AND of MS and MCK and a garbage data bit will be read. As this is a situation of two digital
signals changing simultaneously then unpredictable behavior is to be expected.
To fix this a 3nsec delay was added to MCK with an SDI select in the SPARES field called MCK_SEL. This fixes the issue by
insuring that MS falls before MCK rises so there will be no glitch. But this could be dangerous if the PC board layout adds delay
to MS relative to MCK. The added delay could not be greatly increased as the maximum tolerance delay would then cause an
issue with the last valid data bit.
Case 1: GMSK Clocking Signals Generated by Baseband, TXD_MODE=1, TXF=00
Transmission is initiated by setting the TXST or TXEN pins to a logical high. The baseband will generate a 13/48MHz clock that
is applied to MCK. If SDI bit TXCKINV is low, then on every rising edge of MCK the baseband will assert an NRZ data bit on MDI.
The RF6001 will read this data on every falling edge of MCK if TXCKINV is set. If TXCKINV is set high, the baseband will assert
an NRZ data bit on the falling edge of MCK and the RF6001 will read this data bit on every rising edge of MCK. The diagram
below summarizes the operation of this interface.
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Synthesizer
Fractional
Clock
PHADJ
Phase
Adjust
TX_INV
TX_DE
TX_THP
TX_THN
Interface
Interface
Analog
Digital
TXF
TXCKINV
TXAD
TX_EN
TX_ST
TXI
TXIB/MS
TXQ/MDI
TXQB/MCK
Rev A3 DS050929