RF6001_1 RFMD [RF Micro Devices], RF6001_1 Datasheet - Page 55

• Manufacturer Part Number: RF6001_1
• Description: FRACTIONAL-N RF SYNTHESIZER WITH MODULATOR AND DIGITAL IF FILTER
• Manufacturer: RFMD [RF Micro Devices]

Configuration Register 1 (CFG1)- Address 000000
Rev A3 DS050929
CFG1(16:15)
CFG1(2:0)
Location
CFG1(7:5)
CFG1(17)
CFG1(14)
CFG1(13)
CFG1(12)
CFG1(11)
CFG1(10)
CFG1(9)
CFG1(8)
CFG1(4)
CFG1(3)
TRDC_RX(2:0)
RXMODE(2:0)
PLL_EN(1:0)
Bit Name
GPRS_TX2
GPRS_TX1
SMP_SEL
reserved
reserved
S_MODE
MCKSEL
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UAM
UMS
DBL
Default
000
000
00
0
0
0
0
0
0
0
0
1
0
Selects the A/D RX sampler. Use 0 for interface to an RF27SS with a common
PLL Enable Method Selection
0x=PLL is enabled by RXEN|TXEN|TXST
10=PLL is always disabled
11=PLL is always enabled
Use Alternate mode of PA ramping and data gating. If enabled, the RU_DLY[4:0]
0=disabled
1=enabled
reserved, program to zero (0)
If this bit is set high then the first 16 MCK data bits loaded after MD_DLY1
If programmed high, a nominal delay of 3nsec is added to the MCK input.
reserved, program to zero (0)
Enables GPRS mode 2. In this GPRS mode, the DAC1 will ramp down before
0=GPRS mode 2 disabled
1=GPRS mode 2 enabled
Enables GPRS mode 1. In this GPRS mode, the DAC1 will ramp to the new power
0=GPRS mode 1 is disabled
1=GPRS mode 1 is enabled
Digital RX Interface Mode
000=I and Q data are multiplexed on the DRI pin with 12-bit accuracy, 13MHz
001=I and Q data are presented on the DRI and DRQ pins with 16-bit accuracy,
010=I and Q data are presented on the DRI pin with 16-bit accuracy, 8.667MHz
011=I and Q data are presented on the DRI pin with 16-bit accuracy, 13MHz
100=I and Q data are presented on the DRI pin with 16-bit accuracy, 26MHz
101=I and Q data are presented on the DRI pin with 12-bit accuracy, 26MHz
110=I and Q data are presented on the DRI and DRQ pins with 16-bit accuracy,
111=same as 000
RX Interface Mode
0=analog mode
1=digital mode
SSI Word Rate
0=SSI word rate is equal to the GSM symbol rate
1=SSI word rate is equal to twice the GSM symbol rate
TRD Receive Mode Settings
When RXEN is high, {GPO3, GPO2, GPO1 pins}=TRDC_RX(2:0) for a period
When RXEN is low, {GPO3, GPO2, GPO1 pins}={GPO3, GPO2, GPO1}.
mode voltage of mid-supply ±200mV. Use 1 for interface to other front-ends
with common mode voltage outside of this range.
and RD_DLY[4:0] registers are used to delay the DAC1 ramp up and ramp
down, respectively, relative to the TXST signal. In addition, user data is gated
into the GMSK modulator while TXST is high. While TXST is low, G_DEF is
gated into the modulator.
expires in serial mode will be filled with G_DGF as opposed to loading data
from the FIFO or serial interface. This is used in serial mode with MS, as the
system needs to know to fill the first 16 bits with the default as the first MS
is blanked. The 16 bits occur only on the first burst of a multiburst transmis-
sion.
ramping to the next power level. Between bursts, the ramp down is initiated
by TXST falling. The ramp up is initiated with TXST rising.
level without ramping down to low power. This mode supports the RF6001
legacy PA ramping modes.
clock rate
13MHz clock rate
clock rate
clock rate
clock rate
clock rate
26MHz clock rate
defined by DC_TIME3, reverts back to normal GPO settings at the end of this
time.
Part of the POLARIS™ TOTAL RADIO™ Solution
Function
RF6001
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