RF6001_1 RFMD [RF Micro Devices], RF6001_1 Datasheet - Page 48

• Manufacturer Part Number: RF6001_1
• Description: FRACTIONAL-N RF SYNTHESIZER WITH MODULATOR AND DIGITAL IF FILTER
• Manufacturer: RFMD [RF Micro Devices]

RF6001
Part of the POLARIS™ TOTAL RADIO™ Solution
Synthesizer Information
Fractional-N Synthesizer
The RF6001 contains a charge-pump based, fractional-N phase locked loop (PLL) for controlling the receive VCO’s on the
RF2722 and the transmit VCO’s on the RF6001. The PLL includes integrated loop filters and automatic calibration systems to
counteract the effects of process and environmental variations, ensuring repeatable locktime and noise performance. The PLL
is intended to use a 26MHz reference frequency signal for operation within GSM Cellular Radio systems, but may be pro-
grammed to use lower frequency reference signals if desired; however, noise performance will degrade if a lower reference fre-
quency is used.
Enabling the PLL
The PLL can be enabled by the TXST, TXEN, or RXEN signals in addition to the PLLEN(1:0) bits. This allows automatic timing of
the complete Polaris chipset warm-up from a single pin in either TX or RX mode.
The PLL interfaces to both the integrated VCO’s on the RF6001 or can interface to an external VCO via the FIN and VT pins. The
VT_EN and VCOSEL bits determine the mode of operation. When VT_EN is set to 0, the internal loop filter is disconnected from
the VT pin. When VCOSEL(1:0) is set to 00, an external VCO can be used with the input through FIN. With VT_EN set to 1, the
internal loop filters are connected and the internal VCO is selected using the VCOSEL(1:0). With VCOSEL(1:0)=10, the inte-
grated VCO1 is active; with the VCOSEL(1:0)=11, the integrated VCO2 is active.
PLL Configuration
The RF6001 PLL provides options for use of internal and external VCO’s, internal or external loop filter, automatic calibrations,
etc. These settings require three 18-bit registers (54-bits). In order to provide rapid switching between operating modes, the
serial interface provides four groups of ‘PLL Preset’ registers. Each group contains three registers. The active PLL Preset regis-
ter group is determined by the PLLSEL(1:0) bits, as shown in the following table.
The PLL Preset registers share the addresses 000101, 000110 and 000111. For example, if PLLSEL(1:0)=00, then the PLL0x
group is active, and address 000101 writes to PLL00, address 000110 writes to PLL01, address 000111 writes to PLL02, and
the PLL will use the settings in PLL00, PLL01 and PLL02.
If PLLSEL(1:0)=10, then the PLL2x group is active, these addresses write to PLL20, PLL21, PLL22, and the PLL will use the
settings in these registers.
Loop Filters
The PLL contains loop filters optimized for the VCO’s it controls. The resistor and capacitor values of the loop filters (and the
DAC filters) are calibrated by an RC Calibration System that runs for up to 20μs when the PLLs or DACs are enabled. The
RC_EN bit in the CAL register determines whether the RC calibration system runs. It is recommended that the RC_EN bit be set
to true (1) always, to allow the system to run each time the PLL or DACs are enabled, to accommodate environmental varia-
tions. The PLL loop filter can be bypassed such that the VT pin will then be directly connected to the output of the PLL charge
pump, using the VT_EN and LPF serial interface bits. In this manner, the PLL can be used with an external VCO and external
loop filter.
Charge Pump Currents
The PLL employs a deadzone-free phase detector for fast, low-jitter locking performance. The base current in the charge pump
can be selected using the CPI(0)bit. With CPI(0) set to 0, the charge pump is in a low current setting for use in receive mode
with the RF2722. With CPI(0) set to 1, the charge pump is in a higher current setting for transmit mode with internal VCO’s.
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PLLSEL(1:0)
00
01
10
11
Active PLL Preset Register Group
PLL0x (PLL00, PLL01, PLL02)
PLL1x (PLL10, PLL11, PLL12)
PLL2x (PLL20, PLL21, PLL22)
PLL3x (PLL30, PLL31, PLL32)
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Rev A3 DS050929