RF6001_1 RFMD [RF Micro Devices], RF6001_1 Datasheet - Page 39

• Manufacturer Part Number: RF6001_1
• Description: FRACTIONAL-N RF SYNTHESIZER WITH MODULATOR AND DIGITAL IF FILTER
• Manufacturer: RFMD [RF Micro Devices]

G_DLY (GMSK delay)
This field will increase the latency of the GMSK modulator in 1/16 symbol increments. The modulator delay can be adjusted
from 12.2qst to 19.95qst.
G_DLY will hold the GMSK modulator in reset until G_DLY expires. The data flow to the modulator is also delayed by the same
amount. This will add latency to the GMSK modulator. During the reset time the data held in the GMSK modulator shift register
is frozen and the output of the modulator is frozen. When G_DLY expires then the shift register loads the new data bit that was
present at the start of G_DLY. The shift register and modulator output are then released.
The G_DLY operation is performed on the occurrence of the first valid data bit of each time slot in a GPRS transmission if
EALGN is true.
If EALGN is false then the G_DLY operation is performed only at the first valid data bit of the first timeslot.
EALGN
The purpose of this bit is to realign the GMSK data flow to the trigger signal if the trigger signal is not on the symbol clock raster
defined by the first rising edge of TX_ST.
If all timing is aligned to the symbol raster then EALGN can be set to zero and timing advances based on the initial rising edge
of TX_ST. In this case the guard time between GPRS bursts will be an integer multiple of symbol times. This represents a timing
slip of ¼ symbol from the ETSI requirement.
If this bit is true then the data clocks used for GMSK are reset on the first valid data bit of each timeslot. In FIFO mode the first
valid data bit occurs when MD_DLY1 or MD_DLY2 time out. In serial mode the first valid data bit occurs on the first falling MCK
edge after MD_DLY1 or MD_DLY2 expire. (G_CNT is ignored) If UAM is true then MD_DLY2 is not used and the trigger point is
then the rise of TX_ST or MD_DLY1 expiring.
When the clocks reset then a phase glitch will occur. In GMSK mode the glitch will be at the modulator output at the end of the
G_DLY interval. This is because GMSK uses a lookup table system and thus resetting the clock glitches the output as soon as
the G_DLY parameter releases the output.
UMS (use MS)
If this bit is set high then the first 16 MCK data bits loaded after MD_DLY1 expires in serial mode will be filled with G_DEF as
opposed to loading data from the FIFO or serial interface. This is used in serial mode with MS as the system needs to know to
fill the first 16 bits with the default as the first MS is blanked. The 16 bits occur ONLY on the first burst of a GPRS transmission.
MD_DLY1 (Modulation Delay 1)
This field sets the delay from the rising edge of TX_ST to the beginning of the modulation.
Counter resolution will be 1/8 symbol time to allow the user to fine tune for the modulator latency. When TX_ST rises the mod-
ulators become active and receive data from the internal default data fields called G_DEF. When MD_DLY expires the GMSK
modulator shifts from the default value to the input data stream.
If FIFO modes are used then the data flow from the FIFO begins when MD_DLY1 expires.
In serial mode if MS is active then the first MS after MD_DLY1 expires is blanked. Thus there are always 16 MCK pulses before
the first rising MS. These first 16 pulses use the internal RF6001 default values. In serial mode, MD_DLY1 only functions if
MCK is supplied by the RF6001.
Rev A3 DS050929
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at ([phone] or [e-mail].
Part of the POLARIS™ TOTAL RADIO™ Solution
RF6001
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