RF6001_1 RFMD [RF Micro Devices], RF6001_1 Datasheet - Page 57

• Manufacturer Part Number: RF6001_1
• Description: FRACTIONAL-N RF SYNTHESIZER WITH MODULATOR AND DIGITAL IF FILTER
• Manufacturer: RFMD [RF Micro Devices]

Configuration Register 3 (CFG3)-Address 000010
Frequency Offset Register (OFFS)-Address 000011
Digital AFC Offset Register (AFCD)-Address 000100
Rev A3 DS050929
CFG3(14:12)
CFG3(11:10)
OFFS(17:0)
AFCD(17:0)
CFG3(3:0)
Location
Location
Location
CFG3(17)
CFG3(16)
CFG3(15)
CFG3(9)
CFG3(8)
CFG3(7)
CFG3(6)
CFG3(5)
CFG3(4)
TRDC_TX(2:0)
PLLSEL(1:0)
AFCD(17:0)
Bit Name
Bit Name
OFFS(17:0)
Bit Name
DAGC(3:0)
reserved
reserved
reserved
reserved
RMPSEL
R1316B
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at ([phone] or [e-mail].
GPO3
GPO2
GPO1
Default
Default
Default
000
00
3h
0
0
0
0
0
0
0
0
0
0
0
General Purpose Output Pins.
TRD Transmit Mode Settings.
PLL Preset Selection, determines the active set of PLLxx registers.
00=PLL00, PLL01, PLL02 registers are active
01=PLL10, PLL11, PLL12 registers are active
10=PLL20, PLL21, PLL22 registers are active
11=PLL30, PLL31, PLL32 registers are active
reserved, program to zero (0)
reserved, program to zero (0)
PA Ramp Table Select, determines the active set of PA ramp registers.
0=ramp table 0 is active
1=ramp table 1 is active
Changes the ramp up and ramp down time from 16quarter symbols to
0=ramp time is 16qst
1=ramp time is 13qst
reserved, program to zero (0)
reserved, program to zero (0)
Digital Gain Control
0000=gain of -18dB
0001=gain of -12dB
...
1100=gain of +54dB
1101=gain of +60dB
1110=gain of +60dB
1111=gain of +60dB
PLL Frequency Offset
Digital AFC offset adjustment for PLLs.
Pins are set high or low as programmed, unless overridden by TR settings,
controlled by TRD, TRDC_RX, TRDC_TX, and the RXEN and TXEN pins.
When TXST is high, {GPO3, GPO2, GPO1 pins}=TRDC_TX(2:0) for a period
defined by TXENU, reverts back to normal GPO settings at the end of this
time.
When TXST is low, {GPO3, GPO2, GPO1 pins}={GPO3, GPO2, GPO1}
13quarter symbols.
Gain is equal to -18dB+DAGC*6dB, from -18dB to +60dB.
Default is 0dB.
The PLL/VCO Lock Frequency is determined by the equation:
F
according to the F
register value. See the AFCD and PLLx0 register descriptions.
The RF6001 takes changes in R and VCODIV into account in the calculation
of F
VCO frequency will be F
VCO frequency with a non 26MHz reference, and F
quency present at the OSCA pin.
This is a two’s component (signed) value. See the OFFS register description
for more information on setting the PLL/VCO frequency.
VCO
VCO
=F
. However, if the frequency present at the OSCA pin is not 26MHz, the
BASE
+OFFS*5kHz+AFCD*26MHz/2^24, where F
Part of the POLARIS™ TOTAL RADIO™ Solution
BASE
(1:0) value, and AFCD is set according to the AFCD
VCO
’=F
VCO
Function
Function
Function
*F
REF
/26MHz, where F
REF
RF6001
is the actual fre-
VCO
BASE
’ is the actual
is set
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