zl50118gag2 Zarlink Semiconductor, zl50118gag2 Datasheet - Page 82

• Manufacturer Part Number: zl50118gag2
• Description: 32 Channel 1 T1/e1 Cesop Processor With Single Ethernet Interface
• Manufacturer: Zarlink Semiconductor

12.6.6
The management interface is common for all inputs and consists of a serial data I/O line and a clock line.
Note 1:
Note 2:
M_MDC Clock Output period
M_MDC high
M_MDC low
M_MDC rise time
M_MDC fall time
M_MDIO setup time (MDC
rising edge)
M_MDIO hold time (M_MDC
rising edge)
M_MDIO Output Delay
(M_MDC rising edge)
Mn_MDIO
Mn_MDC
Refer to Clause 22 in IEEE802.3 (2000) Standard for input/output signal timing characteristics.
Refer to Clause 22C.4 in IEEE802.3 (2000) Standard for output load description of MDIO.
M_MDIO
Signal_Detect
M_MDC
Management Interface Timing
Parameter
RXD[9:0]
RBC1
RBC0
Figure 38 - Management Interface Timing for Ethernet Port - Read
Figure 39 - Management Interface Timing for Ethernet Port - Write
/I/
Table 35 - MAC Management Timing Specification
/S/ /D/ /D/ /D/
Symbol
t
t
tMR
Figure 37 - TBI Receive Timing Diagram
t
t
t
MLO
t
t
MHI
MP
MF
MS
MH
MD
ZL50115/16/17/18/19/20
t
t
RC
RC
t
MS
Zarlink Semiconductor Inc.
/D/
t
MD
1990
Min.
t
900
900
MP
10
0
1
-
-
t
DS
/D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /T/
t
MH
82
t
MHI
t
DH
2000
1000
1000
Typ.
-
-
-
-
-
t
MLO
t
DS
Max.
2010
1100
1100
300
5
5
-
-
t
DH
Units
ns
ns
ns
ns
ns
ns
ns
ns
/R/
Data Sheet
/I/
Note 1
Note 1
Note 1
Note 2
Notes