zl50118gag2 Zarlink Semiconductor, zl50118gag2 Datasheet - Page 59

• Manufacturer Part Number: zl50118gag2
• Description: 32 Channel 1 T1/e1 Cesop Processor With Single Ethernet Interface
• Manufacturer: Zarlink Semiconductor

8.0
8.1
The following lists the intrinsic processing latency of the ZL5011x. The intrinsic processing latency is dependent on
the number of channels in a context for structured operation, as detailed below. However, the intrinsic processing
latency is not dependent on the total number of contexts opened or the total number of channels being processed
by the device.
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End-to-end latency may be estimated as the transmit latency + packet network latency + receive latency. The
transmit latency is the sum of the transmit processing and the number of frames per packet x 125 µs. The receive
latency is the sum of the receive processing and the delay through the jitter buffer which is programmed to
compensate for packet network PDV.
The ZL5011x is capable of creating an extremely low latency connection, with end to end delays of less than
0.5 ms, depending on user configuration.
8.2
The ZL5011x devices support loopback of the TDM circuits and the circuit emulation packets.
TDM loopback is achieved by first packetizing the TDM circuit as normal via the TDM Interface and Payload
Assembly blocks. The packetized data is then routed by the Task Manager back to the same TDM port via the TDM
Formatter and TDM Interface.
Loopback of the emulated services is achieved by redirecting classified packets from the Packet Receive blocks,
back to the packet network. The Packet Transmit blocks are setup to strip the original header and add a new
header directing the packets back to the source.
8.3
The control processor can generate packets directly, allowing it to use the network for out-of-band communications.
This can be used for transmission of control data or network setup information, e.g., routing information. The host
interface can also be used by a local resource for network transmission of processed data.
The device supports dual address DMA transfers of packets to and from the CPU memory, using the host's own
DMA controller. Table 22 illustrates the maximum bandwidths achievable by an external DMA master.
Note 1:
Note 2:
TDM to Packet transmission processing latency less than 125 µs
Packet to TDM transmission processing latency less than 250 µs (unstructured)
Packet to TDM transmission processing latency less than 250 µs (structured, more than 16 channels in
context)
Packet to TDM transmission processing latency less than 375 µs (structured, 16 or less channels in context)
Latency
Loopback Modes
Host Packet Generation
System Features
Maximum bandwidths are the maximum the ZL5011x devices can transfer under host control, and assumes only minimal
packet processing by the host.
Combined figures assume the same amount of data is to be transferred each way.
ZL5011x to CPU only
ZL5011x to CPU only
CPU to ZL5011x only
CPU to ZL5011x only
Combined
Combined
DMA Path
2
2
Table 22 - DMA Maximum Bandwidths
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
Packet Size
>1000 bytes
>1000 bytes
>1000 bytes
60 bytes
60 bytes
60 bytes
59
Max Bandwidth Mbps
11 (5.5 each way)
58 (29 each way)
6.7
50
60
43
1
Data Sheet