zl50118gag2 Zarlink Semiconductor, zl50118gag2 Datasheet - Page 55

• Manufacturer Part Number: zl50118gag2
• Description: 32 Channel 1 T1/e1 Cesop Processor With Single Ethernet Interface
• Manufacturer: Zarlink Semiconductor

Note: To change the packet size of a context, first close the context and then re-open the context with a new packet
size.
6.6
In general, the next processing block for TDM packets is the Protocol Engine. This handles the data-plane
requirements of the main higher level protocols (layers 4 and 5) expected to be used in typical applications of the
ZL5011x family: UDP, RTP, L2TP, CESoPSN, SAToP and CDP. The Protocol Engine can add a header to the
datagram containing up to 24 bytes. This header is largely static information, and is programmed directly by the
CPU. It may contain a number of dynamic fields, including a length field, checksum, sequence number and a
timestamp. The location, and in some cases the length of these fields is also programmable, allowing the various
protocols to be placed at variable locations within the header.
6.7
Packets ready for transmission are queued to the switch fabric interface by the Queue Manager. Four classes of
service are provided, allowing some packet streams to be prioritized over others. On transmission, the Packet
Transmit block appends a programmable header, which has been set up in advance by the control processor.
Typically this contains the data-link and network layer headers (layers 2 and 3), such as Ethernet, IP (versions 4
and 6) and MPLS.
6.8
Incoming data traffic on the packet interface is received by the MACs. The well-formed packets are forwarded to a
packet classifier to determine the destination. When a packet is successfully classified the destination can be the
TDM interface, the LAN interface or the host interface. TDM traffic is then further classified to determine the context
it is intended for.
Each TDM interface context has an individual queue, and the TDM re-formatting process re-creates the TDM
streams from the incoming packet streams. This queue is used as a jitter buffer, to absorb variation in packet delay
across the network. The size of the jitter buffer can be programmed in units of TDM frames (i.e., steps of 125 µs).
There is also a queue to the host interface, allowing a traffic flow to the host CPU for processing. The host’s DMA
controller can be used to retrieve packet data and write it out into the CPU’s own memory.
N octets of data from unstructured stream
Protocol Engine
Packet Transmission
Packet Reception
NOTE: No frame or channel alignment
Figure 19 - ZL50115/16/17/18/19/20 Packet Format - Unstructured Mode
Header
ZL50115/16/17/18/19/20
(if required to meet minimum payload size)
Zarlink Semiconductor Inc.
(added by Packet Transmit)
(added by Protocol Engine)
Ethernet Header
Network Layers
Static Padding
Ethernet FCS
Upper layers
55
Octet N
Octet 1
Octet 2
may include VLAN tagging
e.g. IPv4, IPv6, MPLS
e.g. UDP, L2TP, RTP,
TDM Payload
(constructed by Payload Assembler)
46 to 1500 bytes
may also be placed in the
packet header
CESoPSN, SAToP
Data Sheet