zl50118gag2 Zarlink Semiconductor, zl50118gag2 Datasheet - Page 57

• Manufacturer Part Number: zl50118gag2
• Description: 32 Channel 1 T1/e1 Cesop Processor With Single Ethernet Interface
• Manufacturer: Zarlink Semiconductor

ZL50115/16/17/18/19/20
Data Sheet
7.0
Clock Recovery
One of the main issues with circuit emulation is that the clock used to drive the TDM link is not necessarily linked
into the central office reference clock, and hence may be any value within the tolerance defined for that service.
The reverse link may also be independently timed, and operating at a slightly different frequency. In the
plesiochronous digital hierarchy the difference in clock frequencies between TDM links is compensated for using bit
stuffing techniques, allowing the clock to be accurately regenerated at the remote end of the carrier network.
With a packet network, that connection between the ingress and egress frequency is broken, since packets are
discontinuous in time. From Figure 8, the TDM service frequency f
at the customer premises must be exactly
service
reproduced at the egress of the packet network. The consequence of a long-term mismatch in frequency is that the
queue at the egress of the packet network will either fill up or empty, depending on whether the regenerated clock is
slower or faster than the original. This will cause loss of data and degradation of the service.
The ZL5011x provides a per-stream clock recovery function to reproduce the TDM service frequency at the egress
of the packet network. There are two schemes are employed, depending on the availability of a common reference
clock at each provider edge unit, within the ZL5011x - differential and adaptive.
The adaptive and differential algorithms assume that there are no bit errors in the received packet header sequence
number or timestamp fields. If there are bit errors in the sequence number or timestamp fields, especially in the
most significant bits, then it is likely to cause a temporary degradation of the recovered clock performance. It is
advised to protect packets end-to-end (e.g., by using Ethernet FCS) such that packets with bit errors are discarded
and do not impact the recovered clock performance.
The clock recovery itself is performed by software in the host processor, with support from on-chip hardware to
gather the required statistics.
7.1
Differential Clock Recovery
For applications where the wander characteristics of the recovered clock are very important, such as when the
emulated circuit must be connected into the plesiochronous digital hierarchy (PDH), the ZL5011x also offers a
differential clock recovery technique. This relies on having a common reference clock available at each provider
edge point. Figure 20 illustrates this concept with a common Primary Reference Source (PRS) clock being present
at both the source and destination equipment.
The differential algorithm assumes that the common clock is always present. There is no internal holdover
capability for the common clock source (e.g., TDM_CLKiP). If the availability of the common clock can not be
guaranteed, then it is recommended to use an external DPLL with holdover capability to provide a clock source at
all times. The external DPLL may enter holdover while the common clock is absent to maintain a relatively close
frequency to the original common clock.
In a differential technique, the timing of the TDM service clock is sent relative to the common reference clock. Since
the same reference is available at the packet egress point and the packet size is fixed, the original service clock
frequency can be recovered. This technique is unaffected by any low frequency components in the packet delay
variation. The disadvantage is the requirement for a common reference clock at each end of the packet network,
which could either be the central office TDM clock, or provided by a global position system (GPS) receiver.
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Zarlink Semiconductor Inc.