zl50118gag2 Zarlink Semiconductor, zl50118gag2 Datasheet - Page 40

• Manufacturer Part Number: zl50118gag2
• Description: 32 Channel 1 T1/e1 Cesop Processor With Single Ethernet Interface
• Manufacturer: Zarlink Semiconductor

4.6.2
All JTAG Interface signals are 5 V tolerant, and conform to the requirements of IEEE1149.1 (2001).
4.7
The following unused inputs must be tied low or high as appropriate.
TEST_MODE[2:0]
JTAG_TRST
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
IC_GND
IC_VDD_IO
Miscellaneous Inputs
Signal
Signal
Signal
JTAG Interface
Table 12 - Administration/Control Interface Package Ball Definition
Table 14 - Miscellaneous Inputs Package Ball Definitions
W11, Y11, Y19, AA19, AB18
L22
I/O
I D
I/O
I U
I U
I U
O
I
[2]
[1]
[0]
Y18
V20
U20
AA18
W20
Table 13 - JTAG Interface Package Ball Definition
Package Balls
AB17
Y17
AA17
ZL50115/16/17/18/19/20
Package Balls
Package Balls
Zarlink Semiconductor Inc.
40
Internally connected. Tie to GND.
Internally connected. Tie to VDD_IO.
Test Mode input - ensure these pins are tied
to ground for normal operation.
000 SYS_NORMAL_MODE
001-010 RESERVED
011 SYS_TRISTATE_MODE
100-111 RESERVED
JTAG Reset. Asynchronous reset. In normal
operation this pin should be pulled low.
Recommend external pull-down.
JTAG Clock - maximum frequency is
25 MHz, typically run at 10 MHz. In normal
operation this pin should be pulled either
high or low. Recommend external pull-down.
JTAG test mode select. Synchronous to
JTAG_TCK rising edge. Used by the Test
Access Port controller to set certain test
modes.
JTAG test data input. Synchronous to
JTAG_TCK.
JTAG test data output. Synchronous to
JTAG_TCK.
Description
Description
Description
Data Sheet