zl50118gag2 Zarlink Semiconductor, zl50118gag2 Datasheet
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... Ball PBGA** trays, bake & dry pack ZL50116GAG2 324 Ball PBGA** trays, bake & dry pack ZL50117GAG2 324 Ball PBGA** trays, bake & dry pack ZL50118GAG2 324 Ball PBGA** trays, bake & dry pack ZL50119GAG2 324 Ball PBGA** trays, bake & dry pack ZL50120GAG2 324 Ball PBGA** trays, bake & ...
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... TDM over Cable • TDM over WiFi (802.11x) • TDM over WiMAX (802.16) • Fibre To The Premises G/E-PON • Layer 2 VPN services • Customer-premise and Provider Edge Routers and Switches • Ethernet and IP based IADs ZL50115/16/17/18/19/20 2 Zarlink Semiconductor Inc. Data Sheet ...
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... Payload Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.5.1 Structured Payload Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.5.1.1 Payload Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.5.2 Unstructured Payload Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.6 Protocol Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.7 Packet Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.8 Packet Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.9 TDM Formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.10 Ethernet Traffic Aggregation (ZL50118/19/20 only 7.0 Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.1 Differential Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.2 Adaptive Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.0 System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.1 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 ZL50115/16/17/18/19/20 Table of Contents 3 Zarlink Semiconductor Inc. Data Sheet ...
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... PAC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.6 Packet Interface Timing 12.6.1 MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.6.2 MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12.6.3 GMII Transmit Timing 12.6.4 GMII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 12.6.5 TBI Interface Timing 12.6.6 Management Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12.7 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.8 System Function Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.9 JTAG Interface Timing 13.0 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 ZL50115/16/17/18/19/20 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 14.1 High Speed Clock & Data Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 14.1.1 GMAC Interface - Special Considerations During Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.1.2 TDM Interface - Special Considerations During Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.1.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.2 CPU TA Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 15.0 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 15.1 External Standards/Specifications 15.2 Zarlink Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 16.0 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 ZL50115/16/17/18/19/20 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 41 - CPU Write - MPC8260 Figure 42 - CPU DMA Read - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 43 - CPU DMA Write - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 44 - JTAG Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 45 - JTAG Clock and Reset Timing Figure 46 - ZL50115/16/17/18/19/20 Power Consumption Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 47 - CPU_TA Board Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ZL50115/16/17/18/19/20 List of Figures 6 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 32 - GMII Transmit Timing - 1000 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 33 - GMII Receive Timing - 1000 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 34 - TBI Timing - 1000 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 35 - MAC Management Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 36 - CPU Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 37 - System Clock Timing Table 38 - JTAG Interface Timing ZL50115/16/17/18/19/20 List of Tables 7 Zarlink Semiconductor Inc. Data Sheet ...
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... Update Power Up Sequence Updated values for Updated TXD[9:0] output delay Updated Section 12.6.6 Management Interface Timing (M_MDIO hold time and Figure 39) Added mode details in Figure 40 and Figure 41 Added the CPU_TA assertion time 8 Zarlink Semiconductor Inc. Data Sheet Change and t in Table 32 ER ...
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... MPC8260. Polarity of CPU_DREQ and CPU_SDACK remains programmable through API. Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to conform with default MPC8260. Polarity of CPU_DREQ and CPU_SDACK remains programmable through API. Added 5 kohm pulldown recommendation to GPIO signals. 9 Zarlink Semiconductor Inc. Data Sheet Change Change Change Change ...
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... Mbps MII or 1000 Mbps GMII/TBI 100 Mbps MII or 1000 Mbps GMII/TBI 100 Mbps MII or 1000 Mbps GMII/TBI 100 Mbps MII or 1000 Mbps GMII/TBI 10 Zarlink Semiconductor Inc. Data Sheet Customer Side Packet Interface None None None 100 Mbps MII 100 Mbps MII ...
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... A comprehensive evaluation system is available upon request from your local Zarlink representative or distributor. This system includes the CESoP processor, various TDM interfaces and a fully featured evaluation software GUI that will run on a Windows PC. ZL50115/16/17/18/19/20 11 Zarlink Semiconductor Inc. Data Sheet ...
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... The ZL5011x will be packaged in a PBGA device. Features: • Body Size: • Ball Count: • Ball Pitch: • Ball Matrix: • Ball Diameter: • Total Package Thickness: ZL50115/16/17/18/19/ (typ) 324 1.00 mm (typ 0.60 mm (typ) 2.03 mm (typ) 12 Zarlink Semiconductor Inc. Data Sheet ...
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... E IC PLL_PRI IC IC_GND IC GND GND A1VDD_PL IC IC SYSTEM_D SYSTEM_R GPIO[1] GPIO[2] L1 EBUG ST IC GPIO[0] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[10] 13 Zarlink Semiconductor Inc. Data Sheet GND CPU_DATA[ CPU_DATA[ CPU_DATA[ CPU_DATA[ CPU_DATA[ CPU_SDAC VDD_IO 19] 12 CPU_DATA[ CPU_DATA[ CPU_DATA[ ...
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... E IC PLL_PRI IC IC_GND IC GND GND A1VDD_PL IC IC SYSTEM_D SYSTEM_R GPIO[1] GPIO[2] L1 EBUG ST IC GPIO[0] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[10] 14 Zarlink Semiconductor Inc. Data Sheet GND CPU_DATA[ CPU_DATA[ CPU_DATA[ CPU_DATA[ CPU_DATA[ CPU_SDAC VDD_IO 19] 12 CPU_DATA[ CPU_DATA[ CPU_DATA[ ...
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... E IC PLL_PRI IC IC_GND IC GND GND A1VDD_PL IC IC SYSTEM_D SYSTEM_R GPIO[1] GPIO[2] L1 EBUG ST IC GPIO[0] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[10] 15 Zarlink Semiconductor Inc. Data Sheet GND CPU_DATA[ CPU_DATA[ CPU_DATA[ CPU_DATA[ CPU_DATA[ CPU_SDAC VDD_IO 19] 12 CPU_DATA[ CPU_DATA[ CPU_DATA[ ...
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... IC PLL_PRI IC IC_GND IC GND GND A1VDD_PL IC IC SYSTEM_D SYSTEM_R GPIO[1] GPIO[2] L1 EBUG GPIO[0] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[10] 16 Zarlink Semiconductor Inc. Data Sheet GND CPU_DATA[ CPU_DATA[ CPU_DATA[ CPU_DATA[ CPU_DATA[ CPU_SDAC 23] 19] 12 CPU_DATA[ CPU_DATA[ CPU_DATA[ CPU_DATA[ ...
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... IC PLL_PRI IC IC_GND IC GND GND A1VDD_PL IC IC SYSTEM_D SYSTEM_R GPIO[1] GPIO[2] L1 EBUG GPIO[0] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[10] 17 Zarlink Semiconductor Inc. Data Sheet GND CPU_DATA[ CPU_DATA[ CPU_DATA[ CPU_DATA[ CPU_DATA[ CPU_SDAC 23] 19] 12 CPU_DATA[ CPU_DATA[ CPU_DATA[ CPU_DATA[ ...
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... IC PLL_PRI IC IC_GND IC GND GND A1VDD_PL IC IC SYSTEM_D SYSTEM_R GPIO[1] GPIO[2] L1 EBUG GPIO[0] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[10] 18 Zarlink Semiconductor Inc. Data Sheet GND CPU_DATA[ CPU_DATA[ CPU_DATA[ CPU_DATA[ CPU_DATA[ CPU_SDAC 23] 19] 12 CPU_DATA[ CPU_DATA[ CPU_DATA[ CPU_DATA[ ...
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... VDD_IO GND GND GND NC M1_TXD[0] M1_TXD[0] NC M1_TXD[1] M1_TXD[1] M0_CRS M0_CRS M0_CRS M0_RXD[0] M0_RXD[0] M0_RXD[0] M0_RBC1 M0_RBC1 M0_RBC1 19 Zarlink Semiconductor Inc. Data Sheet ZL50119 ZL50120 Variant Signal Name VDD_IO All DEVICE_ID[4] All CPU_DATA[28] All CPU_DATA[24] All GND All CPU_DATA[23] All GND All ...
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... CPU_DATA[6] NC M1_RXD[0] M1_RXD[0] NC M1_RXD[2] M1_RXD[2] VDD_IO VDD_IO VDD_IO NC M1_RXDV M1_RXDV M0_RXER M0_RXER M0_RXER VDD_IO VDD_IO VDD_IO 20 Zarlink Semiconductor Inc. Data Sheet ZL50119 ZL50120 Variant Signal Name M0_RBC0 All M1_TXD[3] ZL50118/19/20 M0_RXCLK All M0_TXD[7] All M0_TXD[4] All M0_TXD[0] All VDD_IO All VDD_IO ...
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... GND GND GND GND GND GND GND GND GND VDD_CORE VDD_CORE VDD_CORE CPU_DATA[5] CPU_DATA[5] CPU_DATA[5] CPU_DATA[3] CPU_DATA[3] CPU_DATA[3] 21 Zarlink Semiconductor Inc. Data Sheet ZL50119 ZL50120 Variant Signal Name M0_RXD[5] All VDD_CORE All M1_RXD[3] ZL50118/19/20 CPU_DATA[30] All CPU_DATA[21] All CPU_DATA[15] All CPU_DATA[14] ...
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... GND GND GND GND GND GND GND GND GND GND CPU_TS_ALE CPU_TS_ALE CPU_TS_ALE CPU_WE CPU_WE CPU_WE CPU_OE CPU_OE CPU_OE 22 Zarlink Semiconductor Inc. Data Sheet ZL50119 ZL50120 Variant Signal Name CPU_IREQ0 All NC All NC All VDD_CORE All GND All NC All GND All GND ...
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... CPU_ADDR[20] TDM_STI[1] NC TDM_STI[1] TDM_CLKI[0] TDM_CLKI[0] TDM_CLKI[0] TDM_STO[1] NC TDM_STO[1] TDM_CLKI[1] NC TDM_CLKI[1] VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO 23 Zarlink Semiconductor Inc. Data Sheet ZL50119 ZL50120 Variant Signal Name TDM_STO[3] ZL50117/20 TDM_STI[3] ZL50117/20 VDD_IO All GND All TDM_STO[2] ZL50117/20 GND All GND All GND ...
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... VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_CORE VDD_CORE VDD_CORE VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_CORE VDD_CORE VDD_CORE 24 Zarlink Semiconductor Inc. Data Sheet ZL50119 ZL50120 Variant Signal Name CPU_ADDR[14] All CPU_ADDR[16] All TDM_CLKO[1] ZL50116/17/19/20 TDM_FRMI_REF All VDD_IO All TDM_STI[0] All VDD_CORE ...
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... VDD_IO VDD_IO GND GND GND VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO GND GND GND A1VDD_PLL1 A1VDD_PLL1 A1VDD_PLL1 25 Zarlink Semiconductor Inc. Data Sheet ZL50119 ZL50120 Variant Signal Name IC All IC All IC_GND All IC All GND All GND All GPIO[8] All GPIO[14] All ...
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... GND GND GND GPIO[0] GPIO[0] GPIO[0] 26 Zarlink Semiconductor Inc. Data Sheet ZL50119 ZL50120 Variant Signal Name IC All VDD_IO All GPIO[3] All GPIO[4] All GPIO[5] All GPIO[6] All GPIO[10] All GPIO[11] All GPIO[13] All ...
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... R2 different identities: U1 ST-BUS: TDM_STi[3:0] H.110: H-MVIP: TDM_HDS[3:0] Triggered on rising edge or falling edge depending on standard. At 8.192 Mbps only stream [0] is used. Stream [0] is used for unstructured J2 or T3/E3 on the ZL50117/20. 27 Zarlink Semiconductor Inc. Data Sheet Description TDM_D[3:0] ...
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... At 8.192 Mbps only stream [0] is used. Stream [0] is used for unstructured J2 or T3/E3 on the ZL50117/20. Package Balls TDM port reference clock input for backplane operation TDM port reference clock output for backplane operation 28 Zarlink Semiconductor Inc. Data Sheet Description TDM_D[3:0] Description ...
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... Indicates the start of a TDM frame by pulsing every 125 µs. Normally will straddle rising edge or falling edge of clock pulse, depending on standard and clock frequency. Auxiliary clock input. Typically connected to AUX_CLKO. Auxiliary clock output. Typically connected to AUX_CLKI. 29 Zarlink Semiconductor Inc. Data Sheet Description TDM_FRAME TDM_F0 TDM_FRAME TDM_F0 ...
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... DPLL. Expected frequency range: 8 kHz - 16.384 MHz. Secondary reference output to optional external DPLL Multiplexed & frequency divided reference output for support of optional external DPLL. Expected frequency range: 8 kHz - 16.384 MHz. 30 Zarlink Semiconductor Inc. Data Sheet Description ...
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... Mn_TXEN Mn_TXER Mn_TXER - Mn_GTX_CLK Table 6 - Packet Interface Signal Mapping - MII to GMII/TBI Note: Mn can be either for ZL5011x variants. ZL50115/16/17/18/19/20 GMII TBI (PCS) Mn_LINKUP_LED Mn_ACTIVE_LED Mn_GIGABIT_LED Mn_REFCLK Mn_RBC0 Mn_RBC1 Mn_RXD[7:0] Mn_RXD[8] Mn_RXD[9] Mn_Signal_Detect - - Mn_TXD[7:0] Mn_TXD[8] Mn_TXD[9] Mn_GTX_CLK 31 Zarlink Semiconductor Inc. Data Sheet ...
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... RBC1). Useful, for example, in the absence of valid serial data. NOTE: In MII mode this pin must be driven with the same clock as M0_RXCLK. GMII/MII - M0_RXCLK. Accepts the following frequencies: 25.0 MHz 125.0 MHz 32 Zarlink Semiconductor Inc. Data Sheet Description Description MII 100 Mbps GMII 1 Gbps ...
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... Normally valid when M0_RXDV is asserted. Can be used in conjunction with M0_RXD when M0_RXDV signal is de-asserted to indicate a False Carrier. TBI - M0_RXD[9] Receive Data. Clocked on the rising edges of M0_RBC0 and M0_RBC1. 33 Zarlink Semiconductor Inc. Data Sheet Description Receive data is clocked at ...
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... ZL5011x will transmit a non-valid symbol, somewhere in the transmitted frame. TBI - M0_TXD[9] Transmit Data. Clocked on rising edge of M0_GTXCLK. GMII/TBI only - Gigabit Transmit Clock Output of a clock for Gigabit operation at 125 MHz. 34 Zarlink Semiconductor Inc. Data Sheet Description MII 100 Mbps ...
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... Transmit Enable. Asserted when the MAC has data to transmit, synchronously to M1_TXCLK with the first pre-amble of the packet to be sent. Remains asserted until the end of the packet transmission. Active high. 35 Zarlink Semiconductor Inc. Data Sheet Description MII 100 Mbps MII 100 Mbps ...
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... AB20 [14] T21 [2] AB19 [13] R21 [12] U22 36 Zarlink Semiconductor Inc. Data Sheet Description Description CPU Data Bus. Bi-directional data bus, synchronously transmitted with CPU_CLK rising edge. NOTE: as with all ports in the ZL5011x device, CPU_DATA[0] is the least significant bit (lsb). CPU Address Bus. Address input from processor to ZL5011x, synchronously transmitted with CPU_CLK rising edge ...
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... Package Balls N21 M21 M22 M20 A21 L21 L19 37 Zarlink Semiconductor Inc. Data Sheet Description CPU Chip Select. Synchronous to rising edge of CPU_CLK and active low. Is asserted with CPU_TS_ALE. Must be asserted with CPU_OE to asynchronously enable the CPU_DATA output during a read, including DMA read ...
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... ZL50115/16/17/18/19/20 Package Balls B22 K22 C22 J22 G20 38 Zarlink Semiconductor Inc. Data Sheet Description CPU Transfer Acknowledge. Driven from tri-state condition on the negative clock edge of CPU_CLK following the assertion of CPU_CS. Active low, asserted from the rising edge of CPU_CLK. For a read, asserted when valid data is available at CPU_DATA ...
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... W15 [1] AA13 Recommend 5 kohm pulldown on these Y15 [0] AB9 signals. 39 Zarlink Semiconductor Inc. Data Sheet Description System Clock Input. The system clock frequency is 100 MHz. The quality of SYSTEM_CLK, or the oscillator that drives SYSTEM_CLK directly impacts the adaptive clock recovery performance. See Section 6.3. ...
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... JTAG_TCK rising edge. Used by the Test Access Port controller to set certain test modes. JTAG test data input. Synchronous to JTAG_TCK. JTAG test data output. Synchronous to JTAG_TCK. Internally connected. Tie to GND. Internally connected. Tie to VDD_IO. 40 Zarlink Semiconductor Inc. Data Sheet Description Description Description ...
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... AA6 AA9 AB3 AB4 AB6 AB8 H22 K21 Y1 Y10 Y12 Zarlink Semiconductor Inc. Data Sheet Description 3.3 V VDD Power Supply for IO Ring 0 V Ground Supply 1.8 V VDD Power Supply for Core Region 1.8 V PLL Power Supply Description Internally connected. Leave open circuit ...
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... ZL50115/16/17/18/19/20 Package Balls Package Balls [4] A10 [3] V19 [2] W18 [1] F3 [0] G2 Table 18 - Device ID Ball Definition 42 Zarlink Semiconductor Inc. Data Sheet Description No connection. Leave open circuit. Description Device ID. ZL50115 = 00000 ZL50116 = 00001 ZL50117 = 00010 ZL50118 = 00011 ZL50119 = 00100 ZL50120 = 00101 ...
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... Customer Premises TDM ~ f service Figure 8 - Leased Line Services Over a Circuit Emulation Link ZL50115/16/17/18/19/20 Carrier Network Packet queue Network TDM to packet f Provider Edge Provider Edge Interworking Interworking Function Function 43 Zarlink Semiconductor Inc. Data Sheet Customer Premises TDM f service ~ Extract Clock service ...
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... The use of CESoP here allows the convergence of voice and data on a single access network based on Ethernet. This convergence on Ethernet, a packet technology, rather than SONET/SDH, a switched circuit technology, provides cost and operational savings. Figure 9 - Remote Concentrator Unit using CESoP ZL50115/16/17/18/19/20 44 Zarlink Semiconductor Inc. Data Sheet ...
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... CESoP traffic from many ONUs and connect them at the CO to the PSTN. The native IP or Ethernet traffic from the ONU would be split off at the OLT and connected to the packet network. Customer Premises Ethernet ONU T1/E1 Ethernet ONU T1/E1 Ethernet ONU T1/E1 ZL50115/16/17/18/19/20 Fiber Links GIGE Over Fiber Optical OLT Splitter CESoP Figure 10 - EPON using CESoP 45 Zarlink Semiconductor Inc. Data Sheet Ethernet IP T1/E1 PSTN ...
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... Wireless LAN Access Point CESoP T1/E1 ZL50115/16/17/18/19/20 WiMAX (802.16) 70 Mbps MAC CESoP Wireless LAN Wi-Fi (802.11) Access Point Wi-Fi MAC 54 Mbps Wi- 100 m MAC CESoP Figure 11 - Wi-Fi and WiMAX using CESoP 46 Zarlink Semiconductor Inc. Data Sheet Wireless LAN Access Point WiMAX CESoP T1/E1 MAC CESoP T1/E1 ...
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... Loop Carrier T1/E1 Broadband DLC Figure 12 - Digital Loop Carrier using CESoP ZL50115/16/17/18/19/20 GIGE Over N x GIGE Fiber Dedicated Central Fiber Links Office GIGE Over N x T1/E1 Fiber CESoP 47 Zarlink Semiconductor Inc. Data Sheet IP Edge Router or Multi-Service Switching Platform IP Central Office Switch (Class 5) PSTN ...
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... CESoP Transparent data flow between TDM equipment CESoP CESoP TDM-Packet conversion conversion packet switched network interworking interworking function function 48 Zarlink Semiconductor Inc. Data Sheet IP Edge Router or Multi-Service Switching Platform IP Central Office Switch (Class 5) PSTN TDM equipment constant bit rate TDM link ...
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... TDM to (TM) to PKT PKT to (TM) to TDM TDM to (TM) to CPU TDM to (TM (TM) to CPU CPU to (TM) to TDM PKT to (TM) to CPU CPU to (TM) to PKT Table 19 - Standard Device Flows 49 Zarlink Semiconductor Inc. Data Sheet Admin. Dual Packet Interface MAC JTAG Test Controller JTAG Interface ...
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... Interface type Bit clock in and out Data in and out Bit clock out Frame pulse out Data in and out Bit clock in Frame in Data in and out 50 Zarlink Semiconductor Inc. Data Sheet Interfaces to Line interface unit Framers TDM backplane (master) Framers TDM backplane (slave) ...
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... Negative 2.048 244 Negative 4.096 244 Negative 16.384 244 Negative 2.048 488 Positive 8.192 122 Positive 51 Zarlink Semiconductor Inc. Data Sheet Frame Boundary Alignment Standard frame clock pulse Rising Straddles MSAN-126 Edge boundary Rev B (Issue 4) Falling Straddles Zarlink Edge ...
Page 52
... The Packet Transmit (PTX) circuit adds Layer 2 and Layer 3 protocol headers. The chosen protocol header combination for addition by the PTX must not exceed 64 bytes. The exception is context 127 (the 128th context), which must not exceed 56 bytes. ZL50115/16/17/18/19/20 PRS PRD DIV SRS SRD DIV 52 Zarlink Semiconductor Inc. Data Sheet PLL_PRI PLL_SE C CLOCK Internal DPLL FRAME ...
Page 53
... Channel 2 Channel x Channel 1 Channel 2 Channel x Static Padding (if required to meet minimum payload size) Ethernet FCS 53 Zarlink Semiconductor Inc. Data Sheet may include VLAN tagging e.g. IPv4, IPv6, MPLS e.g. UDP, L2TP, RTP, CESoPSN, SAToP TDM Payload (constructed by Payload Assembler) may also be placed in the packet header ...
Page 54
... Zarlink Semiconductor Inc. Data Sheet ...
Page 55
... Upper layers (added by Protocol Engine) Octet 1 Octet 2 Octet N Static Padding (if required to meet minimum payload size) Ethernet FCS 55 Zarlink Semiconductor Inc. Data Sheet may include VLAN tagging e.g. IPv4, IPv6, MPLS e.g. UDP, L2TP, RTP, CESoPSN, SAToP TDM Payload (constructed by Payload Assembler 1500 bytes ...
Page 56
... Gigabit Ethernet ports the TDM CESoP traffic may be sent to a higher priority output queue (there are four output queues total) than the native Fast Ethernet traffic. In this way the access to the provider side Gigabit Ethernet port is prioritized for TDM traffic over native Ethernet traffic. ZL50115/16/17/18/19/20 56 Zarlink Semiconductor Inc. Data Sheet ...
Page 57
... The disadvantage is the requirement for a common reference clock at each end of the packet network, which could either be the central office TDM clock, or provided by a global position system (GPS) receiver. ZL50115/16/17/18/19/20 at the customer premises must be exactly service 57 Zarlink Semiconductor Inc. Data Sheet ...
Page 58
... ZL5011x destination node Packets Packets Network Host CPU Figure 20 - Differential Clock Recovery ZL5011x destination node Packets Packets Network Figure 21 - Adaptive Clock Recovery 58 Zarlink Semiconductor Inc. Data Sheet Data LIU Timestamp Dest'n extraction Clock DCO Timing recovery Queue Dest'n Clock DCO Time ...
Page 59
... Combined figures assume the same amount of data transferred each way. ZL50115/16/17/18/19/20 Packet Size >1000 bytes 60 bytes >1000 bytes 60 bytes 2 >1000 bytes 2 60 bytes Table 22 - DMA Maximum Bandwidths 59 Zarlink Semiconductor Inc. Data Sheet 1 Max Bandwidth Mbps 50 6 (29 each way) 11 (5.5 each way) ...
Page 60
... DC DD RST SCLK 8.6 JTAG Interface and Board Level Test Features The JTAG interface is used to access the boundary scan logic for board level production testing. ZL50115/16/17/18/19/20 > 100 µ Figure 22 - Powering Up the ZL5011x 60 Zarlink Semiconductor Inc. Data Sheet DC I/O supply (3.3 V) Core supply (1 ...
Page 61
... All output and I/O output drivers are tri-stated allowing the device to be isolated when testing or debugging the development board. 8.9.2 Test Mode Control The System Test Mode is selected using the dedicated device input bus TEST_MODE[2:0] as follows in Table 23. SYS_NORMAL_MODE SYS_TRI_STATE_MODE ZL50115/16/17/18/19/20 System Test Mode test_mode[2:0] 3’b000 3’b011 Table 23 - Test Mode Control 61 Zarlink Semiconductor Inc. Data Sheet ...
Page 62
... Table 24 - DPLL Input Reference Frequencies ZL50115/16/17/18/19/20 PRD/SRD Frequency at Register Divider Value Ratio (Hex) (Note Zarlink Semiconductor Inc. Data Sheet Maximum Acceptable PLL_PRI or Input Wander PLL_SEC tolerance (MHz) (UI) (Note 2) 0.008 ±1 1.544 ±1023 2.048 ±1023 4.096 ±1023 8.192 ±1023 ...
Page 63
... PRD/SRD Frequency at Register Divider Value Ratio (Hex) (Note 2796 AEC 537 219 699 2BB 63 Zarlink Semiconductor Inc. Data Sheet Maximum Acceptable PLL_PRI or Input Wander PLL_SEC tolerance (MHz) (UI) (Note 2) 16.384 ±1023 6.312 ±1023 0.008 ±1 (on 64k Hz) 0.064 ±1 (on 64 kHz) 0.064 ± ...
Page 64
... MTIE reset bit (MRST bit in the DOM register) can be used. Unlike some designs, switching between references which are at different nominal frequencies do not require intervention such as a system reset. ZL50115/16/17/18/19/20 64 Zarlink Semiconductor Inc. Data Sheet ...
Page 65
... For T1(1.544 MHz), E1(2.048 MHz) and J2(6.312 MHz) input frequencies, the DPLL will accept a wander ±1023UI at 0 conform with the relevant specifications. For the 8 kHz (frame rate) and 64 kHz (the divided pp down output for T3/E3) input frequencies, the wander acceptance is limited to ±1 UI (0.1 Hz). This principle is illustrated in Table 24. ZL50115/16/17/18/19/20 65 Zarlink Semiconductor Inc. Data Sheet ...
Page 66
... There are 2 exceptions to this. a) When reference is 8 kHz, and reference frequency offset relative to the master is small, jitter master clock period is possible holdover mode huge amount of jitter had been present prior to entering holdover, then an additional 2 ns p-p is possible. ZL50115/16/17/18/19/ internal Tapped Delay Line (TDL). 66 Zarlink Semiconductor Inc. Data Sheet ...
Page 67
... ZL50115/16/17/18/19/20 Figure 23 - Jitter Transfer Function Figure 24 - Jitter Transfer Function - Detail 67 Zarlink Semiconductor Inc. Data Sheet ...
Page 68
... unless otherwise stated. SS Symbol Min. Typ 3.0 3.3 DD_IO V 1.65 1.8 DD_CORE V 1.65 1.8 DD_PLL 2 2.0 - IH_5V 68 Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0.5 5.0 V -0.5 2.5 V -0.5 2 -0.5 7.0 V ± ± 2.38 W °C -55 +125 Test Max. Units Condition °C +85 °C 125 3 ...
Page 69
... Symbol Min. Typ 2 1 1.2 T- Min. Typ. Max. 0 Zarlink Semiconductor Inc. Data Sheet Units. Test Condition µA No pull up/down V = 3.6 V DD_IO µA No pull up/down V = 3.6 V DD_IO pF pF µA Input µA Input µA Input at V DD_IO µA ...
Page 70
... C4IH t 110 - C4IL t FOIW 50 - 200 - FOIS FOIH STOD STIS STIH 70 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes 134 ns 134 300 - ns With respect to TDM_CLKi falling edge - ns With respect to TDM_CLKi falling edge 20 ns ...
Page 71
... Channel 127 bit 0 Channel 0 Bit 7 t C2IP t C4IP t FOIH t FOIS t FOIW t STIH t STIS t STOD Ch 31 Bit Bit 7 71 Zarlink Semiconductor Inc. Data Sheet Channel 0 bit 6 t FOIH t STIH t STIS Ch0 bit7 t t STOD STOD Channel 0 bit 7 Channel 0 Bit 6 t STOD Ch 0 Bit 6 ...
Page 72
... STIS STIH Channel 0 Bit 7 t C16OP t FOD t FOD t STIH t STIS B7 t STOD Ch 0 Bit 7 72 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes 68.0 ns 37.0 ns 37.0 ns 251.0 ns 129.0 ns 129 With respect to TDM_CLKo falling edge 5 ns With respect to TDM_CLKo falling edge ...
Page 73
... DV t 102 - DIV t 90 122 Zarlink Semiconductor Inc. Data Sheet Channel 0 Bit 6 t STOD Ch 0 Bit 6 Max. Units Notes 122.074+Φ ns Note 1 Note 2 69+Φ ns 69+Φ Load - Load - 12 pF Note 3 11 ...
Page 74
... C16H C16L HZD 200 244 FW 74 Zarlink Semiconductor Inc. Data Sheet Ts 0 Bit 2 C8L t DOD Ts 0 Bit 2 Max. Units Notes 488.8 ns 268 ns 268 ns 244.4 ns 134 ns 134 ns 61 8.192 Mbps 100 ns At 2.048 Mbps ...
Page 75
... Figure 30 - TDM - H-MVIP Timing Diagram for 16 MHz Clock (8.192 Mbps) ZL50115/16/17/18/19/20 Min. Typ Bit C16H t C16P t t C16L HZD Ch 0 Bit 0 75 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes 150 ns 150 Bit ...
Page 76
... Symbol Min. Typ. t 22.353 CTP t 6.7 CTH t 6.7 CTL t 22.353 CRP t 9.0 CRH t 9.0 CRL CTH t CTP CRH t CRP Zarlink Semiconductor Inc. Data Sheet Max. Units Notes ns DS3 clock DS3 clock CTL t CRL ...
Page 77
... CLO Figure 32 - MII Transmit Timing Diagram 77 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes - Units Notes Max Load = Load = Load = ...
Page 78
... DVS DVH ERS ERH DVS ERS Figure 33 - MII Receive Timing Diagram 78 Zarlink Semiconductor Inc. Data Sheet Units Notes Max CLO CHI t DVH t ERH ...
Page 79
... Min. Typ 2.5 - GCH t 2.5 - GCL GCR GCF Figure 34 - GMII Transmit Timing Diagram 79 Zarlink Semiconductor Inc. Data Sheet Units Notes Max. 8 Load = Load = Load = ...
Page 80
... DVS DVH ERS ERH DVS ERS Figure 35 - GMII Receive Timing Diagram 80 Zarlink Semiconductor Inc. Data Sheet Units Notes Max. 8 CLO CHI t DVH t ERH ...
Page 81
... Table 34 - TBI Timing - 1000 Mbps t DV Figure 36 - TBI Transmit Timing Diagram 81 Zarlink Semiconductor Inc. Data Sheet Units Notes Max. 8 2.4 Load = 10 pF Note 8 ...
Page 82
... MHI t 900 1000 MLO tMR - - MHI Zarlink Semiconductor Inc. Data Sheet /R/ /I/ Max. Units Notes 2010 ns Note 1 1100 ns 1100 Note Note 1 300 ns Note 2 t MLO ...
Page 83
... CKS t 2 CKH t 2 CTV t 2 CWV t 2 CRV t 2 CDV t 3.2 SDV t 3.3 ODV t 3.2 OTV Table 36 - CPU Timing Specification 83 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes Note 1 11.3 ns Note ...
Page 84
... CAH t CES t CTH t CTS t CDS OTV CTV Figure 41 - CPU Write - MPC8260 84 Zarlink Semiconductor Inc. Data Sheet 0 or more cycles 0 or more cycles t CSH t CEH t ODV t SDV t OTV 0 or more cycles 0 or more cycles t CSH t ...
Page 85
... CPU_CS and CPU_OE must BOTH be asserted to enable CWV t CKH t CKS t CSS t CES t CTH t CTS t CDS t CTV t OTV 85 Zarlink Semiconductor Inc. Data Sheet 0 or more cycles 0 or more cycles t CSH t CEH t ODV t SDV t t CTV OTV 0 or more cycles 0 or more cycles t CSH t CEH t CDH ...
Page 86
... The quality of SYSTEM_CLK, or the oscillator that drives SYSTEM_CLK directly impacts the adaptive clock recovery performance. See Section 6.3. ZL50115/16/17/18/19/20 Symbol Min. Typ. CLK - 100 FR CLK - - ACS CLK - - ACA Table 37 - System Clock Timing 86 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes - MHz Note 1, Note 2 and Note 5 ±30 ppm Note 3 ±200 ppm Note 4 ...
Page 87
... TPSU TPH TOPDV TPZ Table 38 - JTAG Interface Timing t LOW t TPSU Don't Care t TOPDV HiZ Figure 44 - JTAG Signal Timing 87 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes With respect to JTAG_CLK falling edge. Note Note Note 2 ...
Page 88
... V core, 3.3V I/O, 25°C and typical processing. ZL50118/19/20 Power Consumption 1.410 1.400 1.390 1.380 1.370 1.360 1.350 1 Figure 46 - ZL50115/16/17/18/19/20 Power Consumption Plot ZL50115/16/17/18/19/20 t LOW t RST Figure 45 - JTAG Clock and Reset Timing (Typical Conditions) 2 Number of Active E1 Unstructured Contexts 88 Zarlink Semiconductor Inc. Data Sheet t HIGH t RSTSU 3 4 ...
Page 89
... AC potential placing guard traces between the signals usually held ground potential. Particular effort should be made to minimize crosstalk from ZL5011x outputs and ensuring fast rise time to these inputs. ZL50115/16/17/18/19/20 89 Zarlink Semiconductor Inc. Data Sheet ...
Page 90
... Particular effort should be made to minimize crosstalk from ZL5011x outputs and ensuring fast rise time to these inputs. In Summary: • Place series termination resistors as close to the pins as possible • minimize output capacitance • Keep common interface traces close to the same length to avoid skew • Protect input clocks and signals from crosstalk ZL50115/16/17/18/19/20 90 Zarlink Semiconductor Inc. Data Sheet ...
Page 91
... TA input to the processor recommended that the logic is fitted close to the ZL5011x and that the clock to the 74LCX74 is derived from the same clock source as that input to the ZL5011x. ZL50115/16/17/18/19/20 + 3V3 R1 4K7 Q D CPU_CS to ZL5011x Figure 47 - CPU_TA Board Circuit 91 Zarlink Semiconductor Inc. Data Sheet +3V3 R2 4K7 CPU_TA to CPU ...
Page 92
... RFC5086; Structure-Aware Time Division Multiplexed (TDM) Circuit Emulation - Service over Packet Switched Network (CESoPSN) • RFC4553; Structure-Agnostic TDM over Packet (SAToP) • ITU-T Y.1413 TDM-MPLS Network Interworking 15.2 Zarlink Standards • MSAN-126 Revision B, Issue 4; ST-BUS Generic Device Specification ZL50115/16/17/18/19/20 92 Zarlink Semiconductor Inc. Data Sheet ...
Page 93
... Multi Protocol Label Switching MTIE Maximum Time Interval Error MVIP Multi-Vendor Integration Protocol (a TDM bus standard) PDH Plesiochronous Digital Hierarchy PLL Phase Locked Loop PRS Primary Reference Source PRX Packet Receive PSTN Public Switched Telephone Circuit ZL50115/16/17/18/19/20 93 Zarlink Semiconductor Inc. Data Sheet ...
Page 94
... ST BUS Standard Telecom Bus, a standard interface for TDM data streams TDL Tapped Delay Line TDM Time Division Multiplexing UDP User Datagram Protocol (RFC 768) UI Unit Interval VLAN Virtual Local Area Network WFQ Weighted Fair Queuing ZL50115/16/17/18/19/20 94 Zarlink Semiconductor Inc. Data Sheet ...