zl50118gag2 Zarlink Semiconductor, zl50118gag2 Datasheet - Page 39

• Manufacturer Part Number: zl50118gag2
• Description: 32 Channel 1 T1/e1 Cesop Processor With Single Ethernet Interface
• Manufacturer: Zarlink Semiconductor

4.5
All System Function Interface signals are 5 V tolerant.
The core of the chip will be held in reset for 16383 SYSTEM_CLK cycles after SYSTEM_RST has gone HIGH to
allow the PLL’s to lock. No chip access should occur at this time.
4.6
4.6.1
All Administration, Control and Test Interface signals are 5 V tolerant.
SYSTEM_CLK
SYSTEM_RST
SYSTEM_DEBUG
GPIO[15:0]
System Function Interface
Test Facilities
Signal
Administration, Control and Test Interface
Signal
Table 12 - Administration/Control Interface Package Ball Definition
Table 11 - System Function Interface Package Ball Definition
OT
I/O
ID/
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
I/O
I
I
I
W13
AA12
AA11
W17
Y16
AB16
AA16
AB15
AB14
W15
Y15
ZL50115/16/17/18/19/20
Package Balls
Package Balls
Zarlink Semiconductor Inc.
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
39
AA15
AB13
AB12
AB11
AB10
AA14
AA13
AB9
General Purpose I/O pins. Connected to an
internal register, so customer can set
user-defined parameters. Bits [4:0] reserved
at start-up or reset for memory TDL setup.
See the ZL50115/16/17/18/19/20
Programmers Model for more details.
Recommend 5 kohm pulldown on these
signals.
System Clock Input. The system clock
frequency is 100 MHz. The quality of
SYSTEM_CLK, or the oscillator that
drives SYSTEM_CLK directly impacts
the adaptive clock recovery
performance. See Section 6.3.
System Reset Input. Active low. The
system reset is asynchronous, and
causes all registers within the ZL5011x
to be reset to their default state.
Recommend external pull-up.
System Debug Enable. This is an
asynchronous
de-asserted,
assertion of the debug-freeze command,
regardless of the internal state of
registers, or any error conditions. Active
high. Recommend external pull-down.
Description
Description
prevents
signal
the
that,
Data Sheet
software
when