zl50118gag2 Zarlink Semiconductor, zl50118gag2 Datasheet - Page 29

• Manufacturer Part Number: zl50118gag2
• Description: 32 Channel 1 T1/e1 Cesop Processor With Single Ethernet Interface
• Manufacturer: Zarlink Semiconductor

TDM_FRMi_REF
TDM_FRMo_REF
AUX_CLKI
AUX_CLKO
Signal
OT
I/O
I D
I D
O
T3
W3
L3
L2
Table 4 - TDM Interface Common Pin Definition
ZL50115/16/17/18/19/20
Package Balls
Zarlink Semiconductor Inc.
29
TDM port reference frame input. For
different standards this pin is given a
different identity:
ST-BUS: TDM_F0i
H.110:
H-MVIP:
Signal is normally active low, but can be
active high depending on standard.
Indicates the start of a TDM frame by
pulsing every 125 µs. Normally will straddle
rising edge or falling edge of clock pulse,
depending on standard and clock frequency.
TDM port reference frame output. For
different standards this pin is given a
different identity:
ST-BUS: TDM_F0o
H.110:
H-MVIP:
Signal is normally active low, but can be
active high depending on standard.
Indicates the start of a TDM frame by
pulsing every 125 µs. Normally will straddle
rising edge or falling edge of clock pulse,
depending on standard and clock frequency.
Auxiliary clock input. Typically connected to
AUX_CLKO.
Auxiliary clock output. Typically connected
to AUX_CLKI.
TDM_FRAME
TDM_FRAME
TDM_F0
TDM_F0
Description
Data Sheet