zl50118gag2 Zarlink Semiconductor, zl50118gag2 Datasheet - Page 28

• Manufacturer Part Number: zl50118gag2
• Description: 32 Channel 1 T1/e1 Cesop Processor With Single Ethernet Interface
• Manufacturer: Zarlink Semiconductor

Note: Speed modes:
Note: All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely left
4.1.2
TDM_STo[3:0]
TDM_CLKi[3:0]
TDM_CLKo[3:0]
TDM_CLKi_REF
TDM_CLKo_REF
2.048 Mbps - 32 channels per stream.
8.192 Mbps - 128 channels per stream.
J2 - 98 channels per stream
E3 - 537 channels per stream
T3 - 699 channels per stream
unconnected if not used.
Signal
Signal
TDM Signals common to ZL50115/16/17/18/19/20
OT
I/O
I D
I/O
I D
O
O
[3]
[2]
[1]
[0]
[3]
[2]
[1]
[0]
[3]
[2]
[1]
[0]
W2
V3
Table 4 - TDM Interface Common Pin Definition
Table 3 - TDM Interface Stream Pin Definition
M2
N1
R4
V1
M1
P1
T1
R3
N2
R1
T2
V2
ZL50115/16/17/18/19/20
Package Balls
Package Balls
Zarlink Semiconductor Inc.
28
TDM port serial data output streams. For
different standards these pins are given
different identities:
ST-BUS: TDM_STo[3:0]
H.110:
H-MVIP: TDM_HDS[3:0]
Triggered on rising edge or falling edge
depending on standard. At 8.192 Mbps only
stream [0] is used. Stream [0] is used for
unstructured J2 or T3/E3 on the
ZL50117/20.
TDM port clock inputs programmable as
active high or low. Can accept frequencies of
1.544 MHz, 2.048 MHz, 4.096 MHz,
8.192 MHz, 6.312 MHz or 16.384 MHz
depending on standard used. At 8.192 Mbps
only stream [0] is used. Stream [0] is used
for unstructured J2 or T3/E3 on the
ZL50117/20.
TDM port clock outputs. Will generate
1.544 MHz, 2.048 MHz, 4.096 MHz,
6.312 MHz, 8.192 MHz or 16.384 MHz
depending on standard used. At 8.192 Mbps
only stream [0] is used. Stream [0] is used
for unstructured J2 or T3/E3 on the
ZL50117/20.
TDM port reference clock input for
backplane operation
TDM port reference clock output for
backplane operation
TDM_D[3:0]
Description
Description
Data Sheet