zl50118gag2 Zarlink Semiconductor, zl50118gag2 Datasheet - Page 61

• Manufacturer Part Number: zl50118gag2
• Description: 32 Channel 1 T1/e1 Cesop Processor With Single Ethernet Interface
• Manufacturer: Zarlink Semiconductor

8.7
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8.8
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8.9
8.9.1
The ZL5011x family supports the following modes of operation.
8.9.1.1
This mode is the device's normal operating mode. Boundary scan testing of the peripheral ring is accessible in this
mode via the dedicated JTAG pins. The JTAG interface is compliant with the IEEE Std. 1149.1-2001; Test Access
Port and Boundary Scan Architecture.
Each variant has it's own dedicated.bsdl file which fully describes it's boundary scan architecture.
8.9.1.2
All output and I/O output drivers are tri-stated allowing the device to be isolated when testing or debugging the
development board.
8.9.2
The System Test Mode is selected using the dedicated device input bus TEST_MODE[2:0] as follows in Table 23.
Direct connection to PowerQUICC™ II (MPC8260) host processor and associated memory, but can
support other processors with appropriate interface logic
TDM Framers and/or Line Interface Units
Ethernet PHY for each MAC port
System clock speed of 100 MHz
Host clock speed of up to 66 MHz
Debug option to freeze all internal state machines
JTAG (IEEE1149) Test Access Port
Fully compatible with MT90880/1/2/3 and ZL50110/11/12/14 Zarlink products
External Component Requirements
Miscellaneous Features
Test Modes Operation
Overview
Test Mode Control
System Normal Mode
System Tri-State Mode
SYS_NORMAL_MODE
SYS_TRI_STATE_MODE
System Test Mode
ZL50115/16/17/18/19/20
Table 23 - Test Mode Control
Zarlink Semiconductor Inc.
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test_mode[2:0]
3’b000
3’b011
Data Sheet