zl50118gag2 Zarlink Semiconductor, zl50118gag2 Datasheet - Page 36

• Manufacturer Part Number: zl50118gag2
• Description: 32 Channel 1 T1/e1 Cesop Processor With Single Ethernet Interface
• Manufacturer: Zarlink Semiconductor

4.4
All CPU Interface signals are 5 V tolerant.
All CPU Interface outputs are high impedance while System Reset is LOW.
M1_TXER
CPU_DATA[31:0]
CPU_ADDR[23:2]
CPU Interface
Signal
Signal
Table 9 - MII Port 1 Interface Package Ball Definition (continued)
I/O
O
C6
I/O
OT
Table 10 - CPU Interface Package Ball Definition
I/
I
[31]
[30]
[29]
[28]
[27]
[26]
[25]
[24]
[23]
[22]
[21]
[20]
[19]
[18]
[17]
[16]
[23]
[22]
[21]
[20]
[19]
[18]
[17]
[16]
[15]
[14]
[13]
[12]
ZL50115/16/17/18/19/20
Package Balls
MII Port 1 (ZL50118/19/20 only)
C16
E19
C18
A11
B16
C19
D20
A12
A14
B17
E20
B18
A16
F20
F21
F22
D21
N20
P22
R22
N22
P21
P20
T22
U21
T21
R21
U22
Package Balls
Zarlink Semiconductor Inc.
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
36
E21
E22
B19
A17
G21
H19
A18
A19
A20
D22
J20
H21
J21
K20
H20
G22
R20
V21
V22
W22
Y22
AA22
AB21
W21
AB20
AB19
Transmit Error. Transmitted synchronously
with respect to M1_TXCLK, and active high.
When asserted (with M1_TXEN also
asserted) the ZL5011x will transmit a
non-valid symbol, somewhere in the
transmitted frame.
CPU Data Bus. Bi-directional data bus,
synchronously transmitted with
CPU_CLK rising edge.
NOTE: as with all ports in the ZL5011x
device, CPU_DATA[0] is the least
significant bit (lsb).
CPU Address Bus. Address input from
processor to ZL5011x, synchronously
transmitted with CPU_CLK rising edge.
NOTE: as with all ports in the ZL5011x
device, CPU_ADDR[2] is the least
significant bit (lsb).
Description
Description
Data Sheet