zl50118gag2 Zarlink Semiconductor, zl50118gag2 Datasheet - Page 77

• Manufacturer Part Number: zl50118gag2
• Description: 32 Channel 1 T1/e1 Cesop Processor With Single Ethernet Interface
• Manufacturer: Zarlink Semiconductor

12.5
12.6
Data for the MII/GMII/TBI packet switching is based on Specification IEEE Std. 802.3 - 2000.
12.6.1
TDM_CLKiP High / Low
Pulsewidth
TDM_CLKiS High / Low
Pulsewidth
TXCLK period
TXCLK high time
TXCLK low time
TXCLK rise time
TXCLK fall time
TXCLK rise to TXD[3:0] active
delay (TXCLK rising edge)
TXCLK to TXEN active delay
(TXCLK rising edge)
TXCLK to TXER active delay
(TXCLK rising edge)
PAC Interface Timing
Packet Interface Timing
TXD[3:0]
MII Transmit Timing
TXCLK
Parameter
TXEN
TXER
Parameter
t
t
EV
DV
Table 30 - MII Transmit Timing - 100 Mbps
Symbol
Figure 32 - MII Transmit Timing Diagram
Table 29 - PAC Timing Specification
t
t
t
CLO
t
t
t
t
t
CHI
CC
CR
DV
ER
Symbol
CF
EV
ZL50115/16/17/18/19/20
t
t
CPP
CSP
Zarlink Semiconductor Inc.
t
ER
Min.
14
14
1
1
1
t
Min.
-
-
-
CC
10
10
77
100 Mbps
Typ.
Typ.
40
-
-
-
-
-
-
-
-
-
t
ER
t
Max.
CL
-
-
Max.
26
26
25
25
25
5
5
-
t
CH
t
EV
Units
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
Load = 25 pF
Load = 25 pF
Load = 25 pF
Data Sheet
Notes
Notes