zl50118gag2 Zarlink Semiconductor, zl50118gag2 Datasheet - Page 8

• Manufacturer Part Number: zl50118gag2
• Description: 32 Channel 1 T1/e1 Cesop Processor With Single Ethernet Interface
• Manufacturer: Zarlink Semiconductor

1.0
The following table captures the changes from the February 2006 issue.
1, 2 and 11
27, 28 and
63 and 66
1, 51,62,
1,10, 11,
Page
49
31
49
50
53
55
56
57
57
58
60
80
82
83
85
Change Summary
Standard
Stratum 3 DPLL
STS-1 stream
Section 4.3
Section 6
Section 6.4
Section 6.5
Section 6.5.2
Section 6.9
Section 7
Section 7.1
Section 7.2
Section 8.5
Section 12.6.3
Section 12.6.5
Section 12.6.6
CPU_TS_ALE and CPU_TA
Item
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
Updated IETF RFC number and standards in general
Updated the description for Stratum 3 DPLL
Remove STS-1 stream
Include more detailed description for the packet interface
Add a note about jumbo packets
Include a paragraph to clarify the support for structure and
unstructure modes at the same time
Include more detailed description for the Payload Assembly
Add a note at the end of the section
Include more detailed description for the TDM formatter
Include more detailed description for Clock Recovery
Include more detailed description for Differential Clock
Recovery
Updated the description of Adaptive Clock Recovery
Update Power Up Sequence
Updated values for t
Updated TXD[9:0] output delay
Updated Section 12.6.6 Management Interface Timing
(M_MDIO hold time and Figure 39)
Added mode details in Figure 40 and Figure 41
Added the CPU_TA assertion time
8
DV
, t
EV
and t
Change
ER
in Table 32
Data Sheet