zl50118gag2 Zarlink Semiconductor, zl50118gag2 Datasheet - Page 66

• Manufacturer Part Number: zl50118gag2
• Description: 32 Channel 1 T1/e1 Cesop Processor With Single Ethernet Interface
• Manufacturer: Zarlink Semiconductor

9.7.2
Intrinsic jitter is the jitter produced by a synchronizer and measured at its output. It is measured by applying a jitter
free reference signal to the input of the device, and measuring its output jitter. Intrinsic jitter may also be measured
when the device is in a non synchronizing mode such as free running or holdover, by measuring the output jitter of
the device. Intrinsic jitter is usually measured with various band-limiting filters, depending on the applicable
standards.
The intrinsic jitter in the DPLL is reduced to less than 1 ns p-p
9.7.3
Jitter tolerance is a measure of the ability of a PLL to operate properly without cycle slips (i.e., remain in lock and/or
regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its
reference. The applied jitter magnitude and the jitter frequency depends on the applicable standards.
The DPLL’s jitter tolerance can be programmed to meet Telcordia GR-1244-CORE DS1 reference input jitter
tolerance requirements.
9.7.4
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter
at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured
with various filters depending on the applicable standards.
Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than
larger ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter
signals (e.g., 75% of the specified maximum jitter tolerance).
The internal DPLL is a first order type 2 component, so a frequency offset doesn’t result in a phase offset. Stratum
3 requires a -3 dB frequency of less than 3 Hz. The nature of the filter results in some peaking, resulting in a -3 dB
frequency of 1.9 Hz and a 0.08 dB peak with a system clock frequency of 100 MHz assuming a p_shift value of 2.
The transfer function is illustrated in Figure 23 and in more detail in Figure 24. Increasing the p_shift value
increases the speed the DPLL will lock to the required frequency and reduces the peak, but also reduces the
tolerance to jitter - so the p_shift value must be programmed correctly to meet Stratum 3 or Stratum 4/4E jitter
transfer characteristics. This is done automatically in the API.
9.8
In order to meet several standards requirements, the phase shift of the DPLL output must be controlled. A potential
phase shift occurs every time the DPLL is re-arranged by changing reference source signal, or the mode. In order
to meet the requirements of Stratum 3, the DPLL will shift phase by no more than 20 ns per re-arrangement.
Additionally the speed at which the change occurs is also critical. A large step change in output frequency is
undesirable. The rate of change is programmable using the skew register, up to a maximum of 15.4 ns / 125 µs
(124 ppm).
1. There are 2 exceptions to this. a) When reference is 8 kHz, and reference frequency offset relative to the master is small, jitter up to 1 master
clock period is possible, i.e. 10 ns p-p. b) In holdover mode, if a huge amount of jitter had been present prior to entering holdover, then an
additional 2 ns p-p is possible.
Maximum Time Interval Error (MTIE)
Intrinsic Jitter
Jitter Tolerance
Jitter Transfer
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
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by an internal Tapped Delay Line (TDL).
Data Sheet