PEB3086HV14XP Infineon Technologies, PEB3086HV14XP Datasheet - Page 95

• Manufacturer Part Number: PEB3086HV14XP
• Manufacturer: Infineon Technologies

Specifications of PEB3086HV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

ISAC-SX
PEB 3086
Description of Functional Blocks
3.7.1
IOM-2 Handler
The IOM-2 handler offers a great flexibility for handling the data transfer between the
different functional units of the ISAC-SX and voice/data devices connected to the IOM-2
interface. Additionally it provides a microcontroller access to all timeslots of the IOM-2
interface via the four controller data access registers (CDA).
Figure 48
shows the
architecture of the IOM-2 handler. For illustrating the functional description it contains all
configuration and control registers of the IOM-2 handler. A detailed register description
can be found in
Chapter
4.4.
The PCM data of the functional units
• Transceiver (TR) and the
• Controller data access (CDA)
• B-channel HDLC controller
can be configured by programming the time slot and data port selection registers
(TSDP). With the TSS bits (Time Slot Selection) the PCM data of the functional units can
be assigned to each of the 32 PCM time slots of the IOM-2 frame. With the DPS bit (Data
Port Selection) the output of each functional unit is assigned to DU or DD respectively.
The input is assigned vice versa. With the data control registers (xxx_CR) the access to
the data of the functional units can be controlled by setting the corresponding control bits
(EN, SWAP).
The IOM-2 handler also provides access to the
• MONITOR channel (MON)
• C/I channels (C/I0,C/I1)
• TIC bus (TIC) and
• HDLC control
The access to these channels is controlled by the registers MON_CR, DCI_CR and
BCH_CR.
The IOM-2 interface with the two Serial Data Strobes (SDS1,2) is controlled by the
control registers IOM_CR, SDS1_CR and SDS2_CR.
The reset configuration of the ISAC-SX IOM-2 handler corresponds to the defined frame
structure and data ports of a master device in IOM-2 terminal mode (see
Figure
46).
Data Sheet
95
2003-01-30