PEB3086HV14XP Infineon Technologies, PEB3086HV14XP Datasheet - Page 144

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PEB3086HV14XP

Manufacturer Part Number
PEB3086HV14XP
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB3086HV14XP

Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
3.8.3.2
The management of the received HDLC frames as affected by the different operating
modes (see
Figure 75
Data Sheet
MDS2 MDS1 MDS0
Description of Symbols:
0
0
1
1
1
Receive Frame Structure
Chapter
Receive Data Flow
1
1
1
1
0
Compared with registers
(D- or B-channel)
Stored in FIFO/registers
1
0
0
1
1
3.8.2) is shown in
MODE
Non
Auto/16
Non
Auto/8
Transparent 0
Transparent 1
Transparent 2
D-channel
B-channel
D-channel
B-channel
D-channel
B-channel
D-channel
B-channel
FLAG
SAP1
SAP2
SAPG
*2)
RAH1
RAH2
Gr.Adr.
*2)
TEI1
TEI2
*2)
RAL1
RAL2
*2)
SAP1
SAP2
SAPG
*2)
RAH1
RAH2
Gr.Adr.
*2)
ADDRESS
*1) CRC optionally stored in RFIFOx if EXMx:RCRC=1
*2) Address optionally stored in RFIFOx if EXMx:SRA=1
*3) Start of the control field in case of an 8 bit address
*4) Content of RSTA register appended at the frameend into RFIFOx
ADDR
Figure
TEI1
TEI2
TEIG
*2)
RAL1
RAL2
Gr.Adr.
*2)
*3)
*3)
TEI1
TEI2
TEIG
*2)
RAL1
RAL2
*2)
144
_
_
CONTROL DATA
CTRL
75.
Description of Functional Blocks
RFIFOx
RFIFOx
RFIFOx
RFIFOx
RFIFOx
I
STATUS
CRC
*1)
*1)
*1)
*1)
*1)
RSTAx
RSTAx
RSTAx
RSTAx
RSTAx
FLAG
21150_13
*4)
*4)
*4)
*4)
*4)
PEB 3086
2003-01-30
ISAC-SX

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