PEB3086HV14XP Infineon Technologies, PEB3086HV14XP Datasheet - Page 114

• Manufacturer Part Number: PEB3086HV14XP
• Manufacturer: Infineon Technologies

Specifications of PEB3086HV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

• A pair of MX and MR in the inactive state for two or more consecutive frames indicates
• A start of a transmission is initiated by the transmitter by setting the MXC bit to ’1’
• The internal MX,MR control indicates or acknowledges a new byte in the MON slot by
• Two frames with the MX-bit in the inactive state indicate the end of transmission.
• Two frames with the MR-bit set to inactive indicate a receiver request for abort.
• The transmitter can delay a transmission sequence by sending the same byte
• Since a double last-look criterion is implemented the receiver is able to receive the
• To control this handshake procedure a collision detection mechanism is implemented
• Monitor data will be transmitted repeatedly until its reception is acknowledged or the
• Two frames with the MX bit in the inactive state indicates the end of a message
• Transmission and reception of monitor messages can be performed simultaneously.
3.7.3.2
In case the ISAC-SX does not detect identical monitor messages in two successive
frames, transmission is not aborted. Instead the ISAC-SX will wait until two identical
bytes are received in succession.
A transmission is aborted of the ISAC-SX if
• an error in the MR handshaking occurs
• a collision on the IOM-2 bus of the MONITOR data or MX bit occurs
• the transmission time-out timer expires
A reception is aborted by the device if
• an error in the MX handshaking occurs or
• an abort request from the opposite device occurs
Data Sheet
an idle state or an end of transmission.
enabling the internal MX control. The receiver acknowledges the received first byte by
setting the MR control bit to ’1’ enabling the internal MR control.
toggling MX,MR from the active to the inactive state for one frame.
continuously. In that case the MX-bit remains active in the IOM-2 frame following the
first byte occurrence. Delaying a transmission sequence is only possible while the
receiver MR-bit and the transmitter MX-bit are active.
MON slot data at least twice (in two consecutive frames), the receiver waits for the
acknowledge of the reception of two identical bytes in two successive frames.
in the transmitter. This is done by making a collision check per bit on the transmitted
MONITOR data and the MX bit.
transmission time-out timer expires.
(EOM).
This feature is used by the ISAC-SX to send back the response before the
transmission from the controller is completed (the ISAC-SX does not wait for EOM
from controller).
Error Treatment
114
Description of Functional Blocks
PEB 3086
2003-01-30
ISAC-SX