PEB3086HV14XP Infineon Technologies, PEB3086HV14XP Datasheet - Page 192

• Manufacturer Part Number: PEB3086HV14XP
• Manufacturer: Infineon Technologies

Specifications of PEB3086HV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

AOE
ARX
Note: An interrupt is only generated if the corresponding mask bit in AUXM is reset. This
For general information please refer to
4.3.3
Value after reset: FF
For general information please refer to
OE7-0 ... Output Enable for AUX7 - AUX0
0: Pin AUX7-0 is configured as output. The value of the corresponding bit in the ATX
register is driven on AUX7-0.
1: Pin AUX7-0 is configured as input. The value of the corresponding bit can be read from
the ARX register.
Note: In NT and LT modes the pins AUX0-2 are not available as I/O pins. If pins AUX7,
4.3.4
Value after reset: (not defined)
AR7-0 ... Auxiliary Receive
The value of AR7-0 always reflects the level at pin AUX7-0 at the time when ARX is read
by the host even if a pin is configured as output. If the mask bit for AUX7, 6 is set in the
MASKA register, no interrupt is generated to the ISAC-SX, however, the current state at
pin AUX7,6 can be read from AR7,6
Data Sheet
configuration is only valid if the corresponding output enable bit in AOE is
disabled.
AUX6 are to be used as interrupt input, OE7, OE6 must be set to 1. If pins AUX7,
AUX5 and AUX4 are not used as I/O pins (see ACFG2), the corresponding OEx
bit cannot be set, but delivers the mode dependent direction (input/output) in that
function upon a read access. If the secondary function is disabled, the direction of
the pin as I/O pin is valid again.
7
7
AOE - Auxiliary Output Enable Register
ARX - Auxiliary Interface Receive Register
OE7
AR7
OE6
AR6
H
OE5
AR5
OE4
AR4
Chapter
Chapter
192
OE3
AR3
3.8.1.
3.8.1.
OE2
AR2
Detailed Register Description
OE1
AR1
0
0
OE0
AR0
RD/WR (3E)
PEB 3086
2003-01-30
ISAC-SX
RD (3F)