PEB3086HV14XP Infineon Technologies, PEB3086HV14XP Datasheet - Page 171

• Manufacturer Part Number: PEB3086HV14XP
• Manufacturer: Infineon Technologies

Specifications of PEB3086HV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

RFBS … Receive FIFO Block Size
Bit 6
0
0
1
1
Note: A change of RFBS will take effect after a transmitter command (CMDR.RMC,
SRA … Store Receive Address
0 … Receive Address isn’t stored in the RFIFOD
1 … Receive Address is stored in the RFIFOD
XCRC … Transmit CRC
0 … CRC is transmitted
1 … CRC isn’t transmitted
RCRC… Receive CRC
0 … CRC isn’t stored in the RFIFOD
1 … CRC is stored in the RFIFOD
ITF… Interframe Time Fill
Selects the inter-frame time fill signal which is transmitted between HDLC-frames.
0 … idle (continuous ’1’)
1 … flags (sequence of patterns: ‘0111 1110’)
Note: ITF must be set to ’0’ for power down mode.
Data Sheet
CMDR.RRES,) has been written
In applications with D-channel access handling (collision resolution), the only
possible inter-frame time fill is idle (continuous ’1’). Otherwise the D-channel on
the S/T-bus cannot be accessed
RFBS
Bit5
0
1
0
1
Block Size Receive FIFO
32 byte
16 byte
8 byte
4 byte
171
Detailed Register Description
PEB 3086
2003-01-30
ISAC-SX