PEB3086HV14XP Infineon Technologies, PEB3086HV14XP Datasheet - Page 147

• Manufacturer Part Number: PEB3086HV14XP
• Manufacturer: Infineon Technologies

Specifications of PEB3086HV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Optionally two additional status conditions can be read by the host:
– XDOV (Transmit Data Overflow), indicating that the data block size has been
– XFW (Transmit FIFO Write Enable), indicating that data can be written to the XFIFOx.
Note: The significant interrupts and commands are underlined as only these are usually
The XFIFO requests service from the microcontroller by setting a bit in the ISTAx
register, which causes an interrupt (XPR, XDU, XMR). The microcontroller can then read
the status register STARx (XFW, XDOV), write data in the FIFO and it can change the
transmit FIFO block size (EXMD.XFBS, for D-channel only) if required.
The instant of the initiation of a transmit pool ready (XPR) interrupt after different transmit
control commands is listed in
Table 20
CMDRx
Register
XTF
XTF & XME
XME
When setting XME the transmitter appends the CRC and the endflag at the end of the
frame. When XTF & XME has been set, the XFIFOx is locked until successful
transmission of the current frame, so a consecutive XPR interrupt also indicates
successful transmission of the frame whereas after XME or XTF the XPR interrupt is
asserted as soon as there is space for one data block in the XFIFOx.
The transfer block size is 32 bytes for D- and B-channel by default, but sometimes, if the
microcontroller has a high computational load, it is useful to increase the maximum
reaction time for an XPR interrupt. However, the threshold can only be changed for D-
channel. The maximum reaction time is:
t
With a selected block size of 16 bytes (D-channel only) an XPR interrupt indicates when
a transmit FIFO space of at least 16 bytes is available to accept further data, i.e. there
are still a maximum of 48 bytes (64 bytes - 16 bytes) to be transmitted. With a 32 bytes
Data Sheet
max
interrupt indications of the transmitter are not cleared by XRES, but have to be cleared
by reading these interutps.
exceeded, i.e. more than 16 or 32 byte (D-channel) or 32 byte (B-channel) were
entered and data was overwritten.
This status flag may be polled instead of or in addition to XPR.
= (XFIFOx size - XFBS) / data transmission rate
used during a normal transmission sequence.
XPR Interrupt (availability of XFIFOx) after XTF, XME Commands
Transmit pool ready (XPR) interrupt initiated ...
as soon as the selected buffer size in the FIFOx is available.
after the successful transmission of the closing flag.
The transmitter always sends an abort sequence.
as soon as the selected buffer size in the FIFO is available, two
consecutive frames share flags.
Table
20.
147
Description of Functional Blocks
PEB 3086
2003-01-30
ISAC-SX