PEB3086HV14XP Infineon Technologies, PEB3086HV14XP Datasheet - Page 52

• Manufacturer Part Number: PEB3086HV14XP
• Manufacturer: Infineon Technologies

Specifications of PEB3086HV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

3.3.3
The ISAC-SX offers the capability to control the start of the multiframe from external
signals, so applications which require synchronization between different S-interfaces are
possible. Such an application is the connection of DECT base stations to PBX line cards.
For this purpose a multiplexed function of the AUX4 pin is used. If the ACFG2.A4SEL is
set to “1” the pin is not used as general pupose I/O pin but as M-bit input (NT, LT-S) or
as M-Bit output (TE, LT-T). The direction input/output of the pin MBIT is automatically
selected with the operation mode.
Figure 18
M-Bit Input (LT-S, NT-Mode)
The MBIT pin can be used to synchronize the multiframe structure between several
S-transceivers. Multiframe generation must be enabled (SQXR1.MFEN=1).
The value of MBIT is sampled at the start of the F-bit of the S-frame.
If the input on MBIT is "1", the multiframe counter is reset to frame no. 20 and as a result,
the bits F
again, the multiframe counter counts 20 frames (starting with frame no. 1) and begins
again autonomously.
If MBIT is kept "1", the multiframe counter is permanently reset and the bits F
stay at logic ZERO (line = “1”). If MBIT becomes "0" for only one S-frame, the multiframe-
counter reaches frame no. 1 at which a logic ONE (line = “0”) is transmitted in the F
M-bit position and the S11 bit is transmitted.
Thus, the M-bit can be used to transfer synchronization pulses of any length between
different S-interfaces.
M-Bit Output (TE, LT-T Mode)
In TE and LT-T mode, the ISAC-SX outputs the value of the M-bit on the MBIT pin.
The value of M should be sampled at the falling edge of FSC.
Data Sheet
Output
M-Bit
A
, M and S are transmitted as logic ZERO (line = “1”). If MBIT becomes "0"
Multiframe Synchronization (M-Bit)
Multiframe Synchronization Using the M-Bit
MBIT
S-transceiver
(TE, LT-T)
S-Interface
52
Description of Functional Blocks
S-transceiver
(LT-S, NT)
MBIT
21150_27
PEB 3086
A
2003-01-30
ISAC-SX
M-Bit
Input
, M and S
A
and